/llvm-project/llvm/lib/CodeGen/ |
H A D | RenameIndependentSubregs.cpp | 182 unsigned SubRegIdx = MO.getSubReg(); in findComponents() local 226 unsigned SubRegIdx = MO.getSubReg(); in rewriteOperands() local 355 unsigned SubRegIdx = MO.getSubReg(); in computeMainRangesFixFlags() local
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H A D | RegisterPressure.cpp | 533 unsigned SubRegIdx = MO.getSubReg(); collectOperandLanes() local 551 pushRegLanes(Register Reg,unsigned SubRegIdx,SmallVectorImpl<RegisterMaskPair> & RegUnits) const pushRegLanes() argument 1235 unsigned SubRegIdx = MO.getSubReg(); findUseBetween() local [all...] |
H A D | VirtRegMap.cpp | 396 unsigned SubRegIdx = MO.getSubReg(); readsUndefSubreg() local
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H A D | StackMaps.cpp | 286 unsigned SubRegIdx = TRI->getSubRegIndex(LLVMRegNum, MOI->getReg()); parseOperand() local
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H A D | MachineCopyPropagation.cpp | 714 unsigned SubRegIdx = TRI->getSubRegIndex(CopyDstReg, MOUse.getReg()); forwardUses() local
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H A D | RegisterCoalescer.cpp | 1791 addUndefFlag(const LiveInterval & Int,SlotIndex UseIdx,MachineOperand & MO,unsigned SubRegIdx) addUndefFlag() argument 1945 unsigned SubRegIdx = MO.getSubReg(); setUndefOnPrunedSubRegUses() local
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H A D | RegAllocFast.cpp | 998 unsigned SubRegIdx = MO.getSubReg(); allocVirtRegUndef() local
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H A D | MachineVerifier.cpp | 2736 const unsigned SubRegIdx = MO->getSubReg(); checkLiveness() local
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/llvm-project/llvm/lib/Target/VE/ |
H A D | VEInstrInfo.cpp | 393 const unsigned SubRegIdx[] = {VE::sub_vm_even, VE::sub_vm_odd}; in copyPhysReg() local 399 const unsigned SubRegIdx[] = {VE::sub_even, VE::sub_odd}; in copyPhysReg() local 330 copyPhysSubRegs(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,const DebugLoc & DL,MCRegister DestReg,MCRegister SrcReg,bool KillSrc,const MCInstrDesc & MCID,unsigned int NumSubRegs,const unsigned * SubRegIdx,const TargetRegisterInfo * TRI) copyPhysSubRegs() argument
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/llvm-project/llvm/lib/Target/X86/ |
H A D | X86FixupBWInsts.cpp | 189 const auto SubRegIdx = TRI->getSubRegIndex(SuperDestReg, OrigDestReg); in getSuperRegDestIfDead() local
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H A D | X86ISelDAGToDAG.cpp | 1691 unsigned SubRegIdx = N->getConstantOperandVal(2); PostprocessISelDAG() local 6037 unsigned SubRegIdx; Select() local [all...] |
/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVRegisterInfo.cpp | 318 unsigned Opcode, SubRegIdx; lowerVSPILL() local 395 unsigned Opcode, SubRegIdx; lowerVRELOAD() local [all...] |
H A D | RISCVISelDAGToDAG.cpp | 370 unsigned SubRegIdx = RISCVTargetLowering::getSubregIndexByMVT(VT, I); selectVLSEG() local 411 unsigned SubRegIdx = RISCVTargetLowering::getSubregIndexByMVT(VT, I); selectVLSEGFF() local 463 unsigned SubRegIdx = RISCVTargetLowering::getSubregIndexByMVT(VT, I); selectVLXSEG() local 2195 unsigned SubRegIdx; Select() local 2251 unsigned SubRegIdx; Select() local [all...] |
H A D | RISCVISelLowering.cpp | 2530 unsigned SubRegIdx = RISCV::NoSubRegister; decomposeSubvectorInsertExtractToSubRegs() local 8483 unsigned SubRegIdx = OrigIdx / ElemsPerVReg; lowerINSERT_VECTOR_ELT() local 8694 unsigned SubRegIdx = OrigIdx / ElemsPerVReg; lowerEXTRACT_VECTOR_ELT() local 10116 unsigned SubRegIdx; lowerINSERT_SUBVECTOR() local 10339 unsigned SubRegIdx; lowerEXTRACT_SUBVECTOR() local [all...] |
/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
H A D | GIMatchTableExecutorImpl.h | 1106 uint16_t SubRegIdx = readU16(); executeMatchTable() local 1290 uint16_t SubRegIdx = readU16(); executeMatchTable() local
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/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 2138 SDValue SubRegIdx = CurDAG->getTargetConstant(PPC::sub_32, dl, MVT::i32); in ExtendToInt64() local 2152 SDValue SubRegIdx = CurDAG->getTargetConstant(PPC::sub_32, dl, MVT::i32); in TruncateToInt32() local 3223 SDValue SubRegIdx = in addExtOrTrunc() local 3233 SDValue SubRegIdx = in addExtOrTrunc() local 5394 SDValue SubRegIdx = CurDAG->getTargetConstant(SubReg, dl, MVT::i32); in Select() local 5447 SDValue SubRegIdx = CurDAG->getTargetConstant(PPC::sub_eq, dl, MVT::i32); Select() local [all...] |
/llvm-project/llvm/utils/TableGen/Common/ |
H A D | CodeGenRegisters.cpp | 487 CodeGenSubRegIndex *SubRegIdx; computeSecondarySubRegs() local 509 if (CodeGenSubRegIndex *SubRegIdx = getSubRegIndex(SubReg)) { computeSecondarySubRegs() local
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/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | TargetRegisterInfo.h | 685 getSubRegisterClass(const TargetRegisterClass * SuperRC,unsigned SubRegIdx) getSubRegisterClass() argument
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/llvm-project/llvm/utils/TableGen/Common/GlobalISel/ |
H A D | GlobalISelMatchTable.h | 2074 const CodeGenSubRegIndex *SubRegIdx; global() variable 2124 const CodeGenSubRegIndex *SubRegIdx; global() variable
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/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelDAGToDAG.cpp | 1198 unsigned SubRegIdx = loadVectorConstant() local
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/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 4787 dl, MVT::i32, SDValue(Ld, 0), SubRegIdx); in Select() local 4800 SDValue SubRegIdx = Select() local
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/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelDAGToDAG.cpp | 1586 SelectLoad(SDNode * N,unsigned NumVecs,unsigned Opc,unsigned SubRegIdx) SelectLoad() argument 1615 SelectPostLoad(SDNode * N,unsigned NumVecs,unsigned Opc,unsigned SubRegIdx) SelectPostLoad() argument
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/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 3334 unsigned SubRegIdx = Subtarget.isABI_N64() ? Mips::sub_32 : 0; emitINSERT_DF_VIDX() local
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/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelDAGToDAG.cpp | 383 unsigned SubRegIdx = SubRegOp->getAsZExtVal(); getOperandRegClass() local
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/llvm-project/llvm/lib/CodeGen/LiveDebugValues/ |
H A D | InstrRefBasedImpl.cpp | 1932 unsigned SubRegIdx = SRI.getSubRegIndex(); performCopy() local
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