Home
last modified time | relevance | path

Searched defs:SubReg (Results 1 – 25 of 74) sorted by relevance

123

/llvm-project/llvm/lib/CodeGen/
H A DLiveVariables.cpp245 for (MCPhysReg SubReg : TRI->subregs_inclusive(DefReg)) in HandlePhysRegUse() local
282 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg, in FindLastRefOrPartRef() local
194 for (MCPhysReg SubReg : TRI->subregs(Reg)) { FindLastPartialDef() local
215 for (MCPhysReg SubReg : TRI->subregs_inclusive(DefReg)) FindLastPartialDef() local
267 for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg)) HandlePhysRegUse() local
330 for (MCPhysReg SubReg : TRI->subregs(Reg)) { HandlePhysRegKill() local
359 for (MCPhysReg SubReg : TRI->subregs(Reg)) { HandlePhysRegKill() local
437 for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg)) HandlePhysRegDef() local
440 for (MCPhysReg SubReg : TRI->subregs(Reg)) { HandlePhysRegDef() local
460 for (MCPhysReg SubReg : TRI->subregs(Reg)) { HandlePhysRegDef() local
475 for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg)) { UpdatePhysRegDefs() local
[all...]
H A DLiveIntervalCalc.cpp58 if (LI.hasSubRanges() || (SubReg != 0 && TrackSubRegs)) { in calculate() local
158 if (SubReg != 0) { in extendToUses() local
H A DDetectDeadLanes.cpp92 unsigned SubReg = MI.getOperand(2).getImm(); in isCrossCopy() local
343 unsigned SubReg = MO.getSubReg(); in determineInitialUsedLanes() local
419 unsigned SubReg = MO.getSubReg(); in isUndefRegAtInput() local
H A DMachineInstrBundle.cpp199 for (MCPhysReg SubReg : TRI->subregs(Reg)) { in finalizeBundle() local
318 unsigned SubReg = MO.getSubReg(); in AnalyzeVirtRegLanesInBundle() local
H A DLiveIntervals.cpp559 unsigned SubReg = MO.getSubReg(); shrinkToUses() local
777 unsigned SubReg = MO.getSubReg(); addKillFlags() local
1019 unsigned SubReg = MO.getSubReg(); updateAllRanges() local
1036 unsigned SubReg = MO.getSubReg(); updateAllRanges() local
1450 unsigned SubReg = MO.getSubReg(); findLastUseBefore() local
1585 unsigned SubReg = MO.getSubReg(); repairOldRegInRange() local
1680 unsigned SubReg = MO.getSubReg(); repairIntervalsInRange() local
[all...]
H A DLiveRangeEdit.cpp140 unsigned SubReg = MO.getSubReg(); in allUsesAvailableAt() local
273 unsigned SubReg = MO.getSubReg(); in useIsKill() local
H A DCriticalAntiDepBreaker.cpp216 for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg)) in PrescanInstruction() local
240 for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg)) { in PrescanInstruction() local
H A DVirtRegMap.cpp563 unsigned SubReg = MO.getSubReg(); rewrite() local
/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp104 static bool isGPR64(unsigned Reg, unsigned SubReg, in isGPR64()
113 static bool isFPR64(unsigned Reg, unsigned SubReg, in isFPR64()
129 unsigned &SubReg) { in getSrcFromCopy()
245 unsigned SubReg; in isProfitableToTransform() local
H A DAArch64RegisterInfo.cpp355 for (MCPhysReg SubReg : in UpdateCustomCallPreservedMask() local
468 for (MCPhysReg SubReg : subregs_inclusive(AArch64::ZA)) in getStrictlyReservedRegs() local
476 for (MCSubRegIterator SubReg(AArch64::ZT0, this, /*self=*/true); in getStrictlyReservedRegs() local
1053 shouldCoalesce(MachineInstr * MI,const TargetRegisterClass * SrcRC,unsigned SubReg,const TargetRegisterClass * DstRC,unsigned DstSubReg,const TargetRegisterClass * NewRC,LiveIntervals & LIS) const shouldCoalesce() argument
[all...]
/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsOptionRecord.cpp74 for (const MCPhysReg &SubReg : MCRegInfo->subregs_inclusive(Reg)) { in SetPhysRegUsed() local
/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNRewritePartialRegUses.cpp180 unsigned Offset = TRI->getSubRegIdxOffset(SubReg) - RShift; in shiftSubReg() argument
86 unsigned SubReg = AMDGPU::NoSubRegister; global() member
426 const unsigned SubReg = MO.getSubReg(); rewriteReg() local
469 unsigned SubReg = SubRegs[MO.getSubReg()].SubReg; rewriteReg() local
[all...]
H A DSIRegisterInfo.h388 getChannelFromSubReg(unsigned SubReg) getChannelFromSubReg() argument
393 getNumChannelsFromSubReg(unsigned SubReg) getNumChannelsFromSubReg() argument
[all...]
H A DSIPreAllocateWWMRegs.cpp133 const unsigned SubReg = MO.getSubReg(); rewriteRegs() local
H A DSIRegisterInfo.cpp1542 Register SubReg = e == 1 buildSpillLoadStore() local
1782 Register SubReg = spillSGPR() local
1836 Register SubReg = spillSGPR() local
1898 Register SubReg = restoreSGPR() local
1931 Register SubReg = restoreSGPR() local
1978 Register SubReg = spillEmergencySGPR() local
2013 Register SubReg = spillEmergencySGPR() local
3029 shouldCoalesce(MachineInstr * MI,const TargetRegisterClass * SrcRC,unsigned SubReg,const TargetRegisterClass * DstRC,unsigned DstSubReg,const TargetRegisterClass * NewRC,LiveIntervals & LIS) const shouldCoalesce() argument
3156 findReachingDef(Register Reg,unsigned SubReg,MachineInstr & Use,MachineRegisterInfo & MRI,LiveIntervals * LIS) const findReachingDef() argument
[all...]
H A DSIFormMemoryClauses.cpp374 for (unsigned SubReg : KilledIndexes) { runOnMachineFunction() local
H A DSIFrameLowering.cpp254 Register SubReg = NumSubRegs == 1 in saveToMemory() local
275 Register SubReg = NumSubRegs == 1 in saveToVGPRLane() local
302 Register SubReg = NumSubRegs == 1 in restoreFromMemory() local
321 Register SubReg = NumSubRegs == 1 in restoreFromVGPRLane() local
H A DR600OptimizeVectorRegisters.cpp194 unsigned SubReg = It.first; RebuildVector() local
/llvm-project/llvm/include/llvm/CodeGen/
H A DLivePhysRegs.h86 for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg)) in addReg() local
/llvm-project/llvm/lib/Target/X86/
H A DX86RegisterInfo.cpp562 Reserved.set(SubReg); in getReservedRegs() local
550 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RSP)) getReservedRegs() local
557 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RIP)) getReservedRegs() local
576 for (const MCPhysReg &SubReg : subregs_inclusive(BasePtr)) getReservedRegs() local
/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenRegisters.cpp266 for (const auto &SubReg : SubRegs) { in inheritRegUnits() local
361 for (const auto &SubReg : Map) in computeSubRegs() local
368 for (const auto &SubReg : SubRegs) { in computeSubRegs() local
488 const CodeGenRegister *SubReg; computeSecondarySubRegs() local
546 for (auto SubReg : NewSubReg->SubRegs) { computeSecondarySubRegs() local
565 for (auto SubReg : SubRegs) computeSuperRegs() local
571 for (auto SubReg : SubRegs) { computeSuperRegs() local
595 for (auto SubReg : SubRegs) addSubRegsPreOrder() local
2174 CodeGenRegister *SubReg = S.second; computeRegUnitLaneMasks() local
[all...]
/llvm-project/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.cpp314 shouldCoalesce(MachineInstr * MI,const TargetRegisterClass * SrcRC,unsigned SubReg,const TargetRegisterClass * DstRC,unsigned DstSubReg,const TargetRegisterClass * NewRC,LiveIntervals & LIS) const shouldCoalesce() argument
/llvm-project/llvm/lib/Target/BPF/
H A DBPFMIPeephole.cpp221 Register SubReg = MovMI->getOperand(1).getReg(); eliminateZExtSeq() local
/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.cpp354 shouldCoalesce(MachineInstr * MI,const TargetRegisterClass * SrcRC,unsigned SubReg,const TargetRegisterClass * DstRC,unsigned DstSubReg,const TargetRegisterClass * NewRC,LiveIntervals & LIS) const shouldCoalesce() argument
/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp381 shouldCoalesce(MachineInstr * MI,const TargetRegisterClass * SrcRC,unsigned SubReg,const TargetRegisterClass * DstRC,unsigned DstSubReg,const TargetRegisterClass * NewRC,LiveIntervals & LIS) const shouldCoalesce() argument

123