Lines Matching defs:SubReg

78     /// Register class required to hold the value stored in the SubReg.
84     unsigned SubReg = AMDGPU::NoSubRegister;
128   /// Find right-shifted by RShift amount version of the SubReg if it exists,
130   unsigned shiftSubReg(unsigned SubReg, unsigned RShift) const;
136   /// Cache for getSubReg method: {Offset, Size} -> SubReg index.
178 unsigned GCNRewritePartialRegUses::shiftSubReg(unsigned SubReg,
180   unsigned Offset = TRI->getSubRegIdxOffset(SubReg) - RShift;
181   return getSubReg(Offset, TRI->getSubRegIdxSize(SubReg));
281     for (auto [SubReg, SRI] : SubRegs)
282       // Check that all registers in MinRC support SRI.SubReg subregister.
283       assert(MinRC == TRI->getSubClassWithSubReg(MinRC, SRI.SubReg));
297   for (auto [SubReg, SRI] : SubRegs) {
298     unsigned SubRegOffset = TRI->getSubRegIdxOffset(SubReg);
299     unsigned SubRegEnd = SubRegOffset + TRI->getSubRegIdxSize(SubReg);
309       CoverSubreg = SubReg;
321   for (auto [SubReg, SRI] : SubRegs)
322     MaxAlign = std::max(MaxAlign, TRI->getSubRegAlignmentNumBits(RC, SubReg));
325   for (auto [SubReg, SRI] : SubRegs) {
326     if (TRI->getSubRegAlignmentNumBits(RC, SubReg) != MaxAlign)
329         std::min(FirstMaxAlignedSubRegOffset, TRI->getSubRegIdxOffset(SubReg));
388     if (unsigned NewSubReg = I->second.SubReg)
424     const unsigned SubReg = MO.getSubReg();
425     assert(SubReg != AMDGPU::NoSubRegister); // Due to [1].
426     LLVM_DEBUG(dbgs() << "  " << TRI->getSubRegIndexName(SubReg) << ':');
428     const auto [I, Inserted] = SubRegs.try_emplace(SubReg);
432       SubRegRC = TRI->getSubRegisterClass(RC, SubReg);
467     unsigned SubReg = SubRegs[MO.getSubReg()].SubReg;
468     MO.setSubReg(SubReg);
469     if (SubReg == AMDGPU::NoSubRegister && MO.isDef())