Lines Matching defs:SubReg
1734 Register SubReg = e == 1
1797 SubReg = Register(getSubReg(ValueReg,
1803 unsigned FinalReg = SubReg;
1816 .addReg(SubReg, getKillRegState(IsKill));
1823 SubReg = TmpIntermediateVGPR;
1839 .addReg(SubReg, getDefRegState(!IsStore) | getKillRegState(IsKill));
1907 MI->readsRegister(SubReg, this)) {
1908 MIB.addReg(SubReg, RegState::Implicit);
1984 Register SubReg =
1999 .addReg(SubReg, getKillRegState(UseKill))
2025 // SubReg carries the "Kill" flag when SubReg == SB.SuperReg.
2038 Register SubReg =
2046 .addReg(SubReg, SubKillState)
2100 Register SubReg =
2107 SB.TII.get(AMDGPU::SI_RESTORE_S32_FROM_VGPR), SubReg)
2133 Register SubReg =
2140 SB.TII.get(AMDGPU::SI_RESTORE_S32_FROM_VGPR), SubReg)
2180 Register SubReg =
2188 .addReg(SubReg, SubKillState)
2215 Register SubReg =
2221 SubReg)
3623 unsigned SubReg,
3745 MachineInstr *SIRegisterInfo::findReachingDef(Register Reg, unsigned SubReg,
3757 LaneBitmask SubLanes = SubReg ? getSubRegIndexLaneMask(SubReg)
3866 unsigned SubReg) const {
3869 return std::min(128u, getSubRegIdxSize(SubReg));
3873 return std::min(32u, getSubRegIdxSize(SubReg));