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Searched defs:SubIdx (Results 1 – 25 of 42) sorted by relevance

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/llvm-project/llvm/lib/CodeGen/
H A DDetectDeadLanes.cpp158 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferUsedLanes() local
162 unsigned SubIdx = MI.getOperand(3).getImm(); in transferUsedLanes() local
182 unsigned SubIdx = MI.getOperand(2).getImm(); in transferUsedLanes() local
232 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferDefinedLanes() local
238 unsigned SubIdx = MI.getOperand(3).getImm(); in transferDefinedLanes() local
250 unsigned SubIdx = MI.getOperand(2).getImm(); in transferDefinedLanes() local
H A DExpandPostRAPseudos.cpp69 unsigned SubIdx = MI->getOperand(3).getImm(); in LowerSubregToReg() local
H A DLiveRangeEdit.cpp186 bool Late, unsigned SubIdx, in rematerializeAt() argument
H A DRegisterCoalescer.cpp1817 updateRegDefsUses(Register SrcReg,Register DstReg,unsigned SubIdx) updateRegDefsUses() argument
2415 const unsigned SubIdx; global() member in __anon87e9921d0311::JoinVals
2589 JoinVals(LiveRange & LR,Register Reg,unsigned SubIdx,LaneBitmask LaneMask,SmallVectorImpl<VNInfo * > & newVNInfo,const CoalescerPair & cp,LiveIntervals * lis,const TargetRegisterInfo * TRI,bool SubRangeJoin,bool TrackSubRegLiveness) JoinVals() argument
3110 usesLanes(const MachineInstr & MI,Register Reg,unsigned SubIdx,LaneBitmask Lanes) const usesLanes() argument
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H A DTwoAddressInstructionPass.cpp1868 unsigned SubIdx = mi->getOperand(3).getImm(); runOnMachineFunction() local
1954 unsigned SubIdx = MI.getOperand(i+1).getImm(); eliminateRegSequence() local
H A DTargetRegisterInfo.cpp109 return Printable([Reg, TRI, SubIdx, MRI](raw_ostream &OS) { in printReg() argument
H A DTargetInstrInfo.cpp389 unsigned SubIdx, unsigned &Size, in getStackSlotRange() argument
420 Register DestReg, unsigned SubIdx, in reMaterialize() argument
/llvm-project/llvm/lib/Target/ARM/
H A DThumbRegisterInfo.cpp64 emitThumb1LoadConstPool(MachineBasicBlock & MBB,MachineBasicBlock::iterator & MBBI,const DebugLoc & dl,unsigned DestReg,unsigned SubIdx,int Val,ARMCC::CondCodes Pred,unsigned PredReg,unsigned MIFlags) emitThumb1LoadConstPool() argument
84 emitThumb2LoadConstPool(MachineBasicBlock & MBB,MachineBasicBlock::iterator & MBBI,const DebugLoc & dl,unsigned DestReg,unsigned SubIdx,int Val,ARMCC::CondCodes Pred,unsigned PredReg,unsigned MIFlags) emitThumb2LoadConstPool() argument
105 emitLoadConstPool(MachineBasicBlock & MBB,MachineBasicBlock::iterator & MBBI,const DebugLoc & dl,Register DestReg,unsigned SubIdx,int Val,ARMCC::CondCodes Pred,Register PredReg,unsigned MIFlags) const emitLoadConstPool() argument
H A DARMBaseRegisterInfo.cpp498 emitLoadConstPool(MachineBasicBlock & MBB,MachineBasicBlock::iterator & MBBI,const DebugLoc & dl,Register DestReg,unsigned SubIdx,int Val,ARMCC::CondCodes Pred,Register PredReg,unsigned MIFlags) const emitLoadConstPool() argument
/llvm-project/llvm/utils/TableGen/
H A DGlobalISelEmitter.cpp1311 CodeGenSubRegIndex *SubIdx = CGRegs.getSubRegIdx(ChildRec); importExplicitUseRenderer() local
1445 auto SubIdx = inferSubRegIndexForNode(Dst.getChild(1)); createAndImportSubInstructionRenderer() local
1490 auto SubIdx = inferSubRegIndexForNode(SubRegChild); createAndImportSubInstructionRenderer() local
1587 CodeGenSubRegIndex *SubIdx = CGRegs.getSubRegIdx(SubRegInit->getDef()); importExplicitUseRenderers() local
1654 CodeGenSubRegIndex *SubIdx = CGRegs.getSubRegIdx(SubRegInit->getDef()); importExplicitUseRenderers() local
1879 CodeGenSubRegIndex *SubIdx = CGRegs.getSubRegIdx(SubRegInit->getDef()); inferSuperRegisterClass() local
2135 auto SubIdx = inferSubRegIndexForNode(Dst.getChild(1)); runOnPattern() local
2205 auto SubIdx = inferSubRegIndexForNode(SubRegChild); runOnPattern() local
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H A DRegisterBankEmitter.cpp203 for (const auto &SubIdx : RegisterClassHierarchy.getSubRegIndices()) { visitRegisterBankClasses() local
/llvm-project/llvm/lib/Target/X86/
H A DX86TileConfig.cpp183 unsigned SubIdx = IsRow ? X86::sub_8bit : X86::sub_16bit; INITIALIZE_PASS_DEPENDENCY() local
/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenRegisters.h407 getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const { in getSubClassWithSubReg() argument
425 void setSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx, in setSubClassWithSubReg() argument
436 addSuperRegClass(CodeGenSubRegIndex * SubIdx,CodeGenRegisterClass * SuperRC) addSuperRegClass() argument
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H A DCodeGenRegisters.cpp139 CodeGenSubRegIndex *SubIdx = *I; in computeConcatTransitiveClosure() local
547 CodeGenSubRegIndex *SubIdx = getSubRegIndex(SubReg.second); computeSecondarySubRegs() local
1142 getSuperRegClasses(const CodeGenSubRegIndex * SubIdx,BitVector & Out) const getSuperRegClasses() argument
1965 for (unsigned SubIdx = 0, EndIdx = RegUnitSets.size(); SubIdx != EndIdx; pruneUnitSets() local
2313 for (const auto &SubIdx : SubRegIndices) { inferSubClassWithSubReg() local
2347 for (auto &SubIdx : SubRegIndices) { inferMatchingSuperRegClass() local
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H A DCodeGenTarget.cpp181 getSuperRegForSubReg(const ValueTypeByHwMode & ValueTy,CodeGenRegBank & RegBank,const CodeGenSubRegIndex * SubIdx,bool MustBeAllocatable) const getSuperRegForSubReg() argument
/llvm-project/llvm/lib/MC/
H A DMCRegisterInfo.cpp108 MCRegisterInfo::getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, in getMatchingSuperReg() argument
/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp476 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); in ConstrainForSubReg() argument
525 unsigned SubIdx = Node->getConstantOperandVal(1); EmitSubregNode() local
581 unsigned SubIdx = N2->getAsZExtVal(); EmitSubregNode() local
680 unsigned SubIdx = Op->getAsZExtVal(); EmitRegSequence() local
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/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp209 unsigned SubIdx = X86::NoSubRegister; getSubRegIndex() local
809 unsigned SubIdx; selectTruncOrPtrToInt() local
1269 unsigned SubIdx = X86::NoSubRegister; emitExtractSubreg() local
1307 unsigned SubIdx = X86::NoSubRegister; emitInsertSubreg() local
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H A DX86LegalizerInfo.cpp516 unsigned SubIdx = Query.Opcode == G_EXTRACT ? 0 : 1; X86LegalizerInfo() local
/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h388 getSubRegIndexName(unsigned SubIdx) getSubRegIndexName() argument
408 getSubRegIndexLaneMask(unsigned SubIdx) getSubRegIndexLaneMask() argument
640 getMatchingSuperReg(MCRegister Reg,unsigned SubIdx,const TargetRegisterClass * RC) getMatchingSuperReg() argument
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H A DTargetInstrInfo.h265 isCoalescableExtInstr(const MachineInstr & MI,Register & SrcReg,Register & DstReg,unsigned & SubIdx) isCoalescableExtInstr() argument
522 unsigned SubIdx; global() member
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/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVPrepareFunctions.cpp224 for (std::size_t SubIdx = 1; SubIdx < MatchStr.size(); ++SubIdx) in parseAnnotation() local
/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp761 unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo; in expandExtractElementF64() local
/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp744 SDValue SubIdx = DAG.getNode(ISD::AND, dl, MVT::i32, {Idx, Mask}); in getIndexInWord32() local
1168 SDValue SubIdx = getIndexInWord32(IdxV, ElemTy, DAG); in extractHvxElementReg() local
1229 SDValue SubIdx = getIndexInWord32(IdxV, ElemTy, DAG); insertHvxElementReg() local
1385 unsigned SubIdx = (Idx == 0) ? Hexagon::vsub_lo : Hexagon::vsub_hi; insertHvxSubvectorReg() local
1594 extractSubvector(SDValue Vec,MVT SubTy,unsigned SubIdx,SelectionDAG & DAG) const extractSubvector() argument
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/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrInfo.cpp769 getStackSlotRange(const TargetRegisterClass * RC,unsigned SubIdx,unsigned & Size,unsigned & Offset,const MachineFunction & MF) const getStackSlotRange() argument

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