Lines Matching defs:SubIdx

473 Register InstrEmitter::ConstrainForSubReg(Register VReg, unsigned SubIdx,
476   const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
478   // RC is a sub-class of VRC that supports SubIdx.  Try to constrain VReg
483   // VReg has been adjusted.  It can be used with SubIdx operands now.
489   RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT, isDivergent), SubIdx);
490   assert(RC && "No legal register class for VT supports that SubIdx");
521     unsigned SubIdx = Node->getConstantOperandVal(1);
540         SubIdx == DefSubIdx &&
552       // Reg may not support a SubIdx sub-register, and we may need to
556         Reg = ConstrainForSubReg(Reg, SubIdx,
568         CopyMI.addReg(Reg, 0, SubIdx);
570         CopyMI.addReg(TRI->getSubReg(Reg, SubIdx));
577     unsigned SubIdx = N2->getAsZExtVal();
580     // the largest legal register class supporting SubIdx sub-registers.
584     //   %dst = INSERT_SUBREG %src, %sub, SubIdx
589     //   %dst:SubIdx = COPY %sub
595     SRC = TRI->getSubClassWithSubReg(SRC, SubIdx);
596     assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG");
616     MIB.addImm(SubIdx);
675         unsigned SubIdx = Op->getAsZExtVal();
679         TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);