/llvm-project/llvm/lib/CodeGen/ |
H A D | RegisterCoalescer.h | 42 unsigned SrcIdx = 0; variable
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H A D | TwoAddressInstructionPass.cpp | 1242 tryInstructionTransform(MachineBasicBlock::iterator & mi,MachineBasicBlock::iterator & nmi,unsigned SrcIdx,unsigned DstIdx,unsigned & Dist,bool shouldOnlyCommute) tryInstructionTransform() argument 1448 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) { collectTiedOperands() local 1497 unsigned SrcIdx = TP.first; processTiedPairs() local 1682 unsigned SrcIdx = TO.second[0].first; processStatepoint() local 1834 unsigned SrcIdx = TiedPairs[0].first; runOnMachineFunction() local [all...] |
H A D | TargetRegisterInfo.cpp | 389 unsigned SrcIdx, DefIdx; shareSameRegisterFile() local
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H A D | RegisterCoalescer.cpp | 1292 unsigned SrcIdx = CP.isFlipped() ? CP.getDstIdx() : CP.getSrcIdx(); reMaterializeTrivialDef() local 1983 unsigned SrcIdx = CP.getSrcIdx(); joinCopy() local 3656 unsigned SrcIdx = CP.getSrcIdx(); joinVirtRegs() local [all...] |
H A D | PeepholeOptimizer.cpp | 1919 unsigned SrcIdx = Def->getNumOperands(); getNextSourceFromBitcast() local
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/llvm-project/llvm/lib/Target/X86/ |
H A D | X86MCInstLower.cpp | 1453 getSrcIdx(const MachineInstr * MI,unsigned SrcIdx) getSrcIdx() argument 1614 unsigned SrcIdx = getSrcIdx(MI, 1); printZeroUpperMove() local 1640 unsigned SrcIdx = getSrcIdx(MI, 1); printBroadcast() local 1658 unsigned SrcIdx = getSrcIdx(MI, 1); printExtend() local 1804 unsigned SrcIdx = getSrcIdx(MI, 1); addConstantComments() local 1826 unsigned SrcIdx = getSrcIdx(MI, 1); addConstantComments() local 1847 unsigned SrcIdx = getSrcIdx(MI, 1); addConstantComments() local 1930 unsigned SrcIdx = getSrcIdx(MI, 1); addConstantComments() local 1951 unsigned SrcIdx = getSrcIdx(MI, 1); addConstantComments() local [all...] |
H A D | X86InstrInfo.cpp | 2433 unsigned SrcIdx = (Imm >> 6) & 3; commuteInstructionImpl() local 7230 unsigned SrcIdx = (Imm >> 6) & 3; foldMemoryOperandCustom() local
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H A D | X86ISelLowering.cpp | 5703 unsigned SrcIdx = M / Size; getTargetShuffleAndZeroables() local 6082 unsigned SrcIdx = SrcExtract.getConstantOperandVal(1); getFauxShuffleMask() local 6487 uint64_t SrcIdx = Op.getConstantOperandVal(1); getShuffleScalarElt() local 11941 int SrcIdx = i + Offset; lowerShuffleAsSpecificZeroOrAnyExtend() local 41234 unsigned SrcIdx = (InsertPSMask >> 6) & 0x3; combineTargetShuffle() local 42437 unsigned SrcIdx = (LoMask & 0x2) >> 1; SimplifyDemandedVectorEltsForTargetNode() local 48358 unsigned SrcIdx = Lane * NumSrcEltsPerLane + Elt % NumSrcEltsPerLane; combineVectorPack() local [all...] |
/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | CombinerHelperVectorOps.cpp | 331 int SrcIdx = Mask[Offset]; matchExtractVectorElementWithShuffleVector() local
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H A D | Utils.cpp | 999 for (unsigned SrcIdx = 0; SrcIdx < BV->getNumSources(); ++SrcIdx) { ConstantFoldCountZeros() local 1481 for (unsigned SrcIdx = 0; SrcIdx < BV->getNumSources(); ++SrcIdx) { isConstantOrConstantVector() local
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H A D | CombinerHelper.cpp | 2170 unsigned SrcIdx = MI.getNumOperands() - 1; matchCombineUnmergeConstant() local 2210 unsigned SrcIdx = MI.getNumOperands() - 1; matchCombineUnmergeUndef() local
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/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | R600InstrInfo.cpp | 292 int SrcIdx = getOperandIdx(MI.getOpcode(), Op[0]); getSrcs() local 1374 getFlagOp(MachineInstr & MI,unsigned SrcIdx,unsigned Flag) const getFlagOp() argument
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H A D | AMDGPUInstCombineIntrinsic.cpp | 1297 for (unsigned SrcIdx = 0; SrcIdx < 4; ++SrcIdx) { simplifyAMDGCNMemoryIntrinsicDemanded() local
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H A D | SIFoldOperands.cpp | 251 unsigned SrcIdx = ~0; tryFoldImmWithOpSel() local
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H A D | R600ISelLowering.cpp | 1945 FoldOperand(SDNode * ParentNode,unsigned SrcIdx,SDValue & Src,SDValue & Neg,SDValue & Abs,SDValue & Sel,SDValue & Imm,SelectionDAG & DAG) const FoldOperand() argument
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/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ExpandPseudoInsts.cpp | 500 unsigned PredIdx, DOPIdx, SrcIdx, Src2Idx; expand_DestructiveOp() local [all...] |
/llvm-project/llvm/lib/Transforms/Scalar/ |
H A D | InferAddressSpaces.cpp | 1268 int SrcIdx = U.getOperandNo(); rewriteWithNewAddressSpaces() local
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/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
H A D | LegalizationArtifactCombiner.h | 689 for (unsigned SrcIdx = StartSrcIdx; SrcIdx < StartSrcIdx + NumSrcsUsed; findValueFromBuildVector() local
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/llvm-project/clang/lib/CodeGen/ |
H A D | CGNonTrivialStruct.cpp | 33 enum { DstIdx = 0, SrcIdx = 1 }; enumerator [all...] |
H A D | CGBuiltin.cpp | 21472 Value *SrcIdx = EmitScalarExpr(E->getArg(3)); EmitWebAssemblyBuiltinExpr() local
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/llvm-project/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineVectorOps.cpp | 549 int SrcIdx = in visitExtractElementInst() local
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/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
H A D | AMDGPUAsmParser.cpp | 4345 auto SrcIdx = getNamedOperandIdx(Opcode, SrcName); validateLdsDirect() local 7012 int SrcIdx = 0; cvtExp() local [all...] |
/llvm-project/llvm/lib/CodeGen/LiveDebugValues/ |
H A D | InstrRefBasedImpl.cpp | 2094 LocIdx SrcIdx = MTracker->getSpillMLoc(SpillID); transferSpillOrRestoreInst() local
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/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLoweringHVX.cpp | 862 SmallVectorImpl<int> &SrcIdx) { in buildHvxVectorReg() argument
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/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 5000 int SrcIdx = Mask[DstIdx]; lowerShuffleViaVRegSplitting() local
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