Lines Matching defs:SrcIdx

450   SrcIdx = DstIdx = 0;
499       NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub, SrcIdx,
505       SrcIdx = DstSub;
522     if (DstIdx && !SrcIdx) {
524       std::swap(SrcIdx, DstIdx);
542   std::swap(SrcIdx, DstIdx);
567     assert(!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state.");
581     return TRI.composeSubRegIndices(SrcIdx, SrcSub) ==
1294   unsigned SrcIdx = CP.isFlipped() ? CP.getDstIdx() : CP.getSrcIdx();
1331   // If both SrcIdx and DstIdx are set, correct rematerialization would widen
1336   if (SrcIdx && DstIdx)
1396   Edit.rematerializeAt(*MBB, MII, DstReg, RM, *TRI, false, SrcIdx, CopyMI);
1402   //     %1        = copy %0:subreg ; CopyMI, SrcIdx = 0
1409       assert(SrcIdx == 0 && CP.isFlipped() &&
1410              "Shouldn't have SrcIdx+DstIdx at this point");
2032     unsigned SrcIdx = CP.getSrcIdx();
2035       std::swap(SrcIdx, DstIdx);
2038     if (!TRI->shouldCoalesce(CopyMI, SrcRC, SrcIdx, DstRC, DstIdx,
2463   /// CP.SrcIdx.
3705     unsigned SrcIdx = CP.getSrcIdx();
3707       LaneBitmask Mask = SrcIdx == 0 ? CP.getNewRC()->getLaneMask()
3708                                      : TRI->getSubRegIndexLaneMask(SrcIdx);
3713         LaneBitmask Mask = TRI->composeSubRegIndexLaneMask(SrcIdx, R.LaneMask);