| /llvm-project/polly/lib/Support/ |
| H A D | ISLTools.cpp | 231 isl::set Shifted = shiftDim(Set, Pos, Amount); in shiftDim() local
283 isl::map Shifted = shiftDim(Map, Dim, Pos, Amount); in shiftDim() local
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| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstCombineIntrinsic.cpp | 2224 Value *Shifted = IC.Builder.CreateLShr(Masked, ShiftAmt); instCombineIntrinsic() local
2267 Value *Shifted = IC.Builder.CreateShl(Input, ShiftAmt); instCombineIntrinsic() local
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| H A D | X86ISelLowering.cpp | 27770 SDValue Shifted = LowerSET_ROUNDING() local
[all...] |
| /llvm-project/clang-tools-extra/clangd/refactor/ |
| H A D | Rename.cpp | 1177 Position Shifted = { in buildRenameEdit() local
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| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64AsmPrinter.cpp | 1814 uint64_t Shifted = UOffset >> BitPos; LowerMOVaddrPAC() local
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| H A D | AArch64ISelLowering.cpp | 15053 SDValue Shifted = getVectorBitwiseReduce() local
[all...] |
| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMFrameLowering.cpp | 2930 unsigned Shifted = 0; alignToARMConstant() local
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| /llvm-project/clang/lib/Format/ |
| H A D | Format.cpp | 3593 auto Shifted = tooling::Replacement(FileName, NewOffset, 0, fixCppIncludeInsertions() local
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| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonVectorCombine.cpp | 1852 Value *Shifted = Op.X.Sgn == Signed || Op.Y.Sgn == Signed in processFxpMulChopped() local
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| /llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 3772 auto Shifted = MIRBuilder.buildAShr(Ty, Res, ShiftAmt); lower() local
8088 auto Shifted = MIRBuilder.buildInstr(ShiftOp, {WideTy}, {Mul, ShiftAmt}); lowerSMULH_UMULH() local
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| /llvm-project/llvm/lib/Transforms/Utils/ |
| H A D | SimplifyCFG.cpp | 6871 Value *Shifted = Builder.CreateLShr(TableMask, MaskIndex, "switch.shifted"); SwitchToLookupTable() local
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| /llvm-project/llvm/lib/Analysis/ |
| H A D | ScalarEvolution.cpp | 5939 const SCEV *Shifted = SCEVShiftRewriter::rewrite(BEValue, L, *this); createAddRecFromPHI() local
13363 const SCEV *Shifted = SE.getAddRecExpr(Operands, getLoop(), getNumIterationsInRange() local
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| /llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 12050 SDValue Shifted = DAG.getNode(ISD::SRL, DL, XLenVT, lowerGET_ROUNDING() local
12082 SDValue Shifted = DAG.getNode(ISD::SRL, DL, XLenVT, lowerSET_ROUNDING() local
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| /llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 10628 SDValue Shifted = expandFixedPointMul() local
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| H A D | DAGCombiner.cpp | 8315 MatchRotatePosNeg(SDValue Shifted,SDValue Pos,SDValue Neg,SDValue InnerPos,SDValue InnerNeg,bool HasPos,unsigned PosOpcode,unsigned NegOpcode,const SDLoc & DL) MatchRotatePosNeg() argument
[all...] |
| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 14022 auto Shifted = DAG.getNode(ISD::SRL, DL, MVT::i64, SubNode, generateEquivalentSub() local
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| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 14615 SDValue Shifted = DAG.getZExtOrTrunc(Shift.getOperand(0), performCvtF32UByteNCombine() local
|