| /llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsExpandPseudo.cpp | 181 const unsigned ShiftImm = in expandAtomicCmpSwapSubword() local
490 const unsigned ShiftImm = SEOp == Mips::SEH ? 16 : 24; in expandAtomicBinOpSubword() local
592 const unsigned ShiftImm = SEOp == Mips::SEH ? 16 : 24; in expandAtomicBinOpSubword() local
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| H A D | MipsISelLowering.cpp | 1676 int64_t ShiftImm = 32 - (Size * 8); emitSignExtendToI32InReg() local
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| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 1344 unsigned ShiftImm; emitAddSub_ri() local
1384 emitAddSub_rs(bool UseAdd,MVT RetVT,unsigned LHSReg,unsigned RHSReg,AArch64_AM::ShiftExtendType ShiftType,uint64_t ShiftImm,bool SetFlags,bool WantResult) emitAddSub_rs() argument
1426 emitAddSub_rx(bool UseAdd,MVT RetVT,unsigned LHSReg,unsigned RHSReg,AArch64_AM::ShiftExtendType ExtType,uint64_t ShiftImm,bool SetFlags,bool WantResult) emitAddSub_rx() argument
1577 emitSubs_rs(MVT RetVT,unsigned LHSReg,unsigned RHSReg,AArch64_AM::ShiftExtendType ShiftType,uint64_t ShiftImm,bool WantResult) emitSubs_rs() argument
1707 emitLogicalOp_rs(unsigned ISDOpc,MVT RetVT,unsigned LHSReg,unsigned RHSReg,uint64_t ShiftImm) emitLogicalOp_rs() argument
[all...] |
| H A D | AArch64ISelDAGToDAG.cpp | 2457 uint64_t ShiftImm; isBitfieldExtractOpFromSExtInReg() local
2588 uint64_t ShiftImm; tryBitfieldExtractOpFromSExt() local
[all...] |
| H A D | AArch64ISelLowering.cpp | 22170 unsigned ShiftImm = N->getConstantOperandVal(1); performVectorShiftCombine() local
[all...] |
| /llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 892 unsigned ShiftImm; // shift for OffsetReg. member
902 unsigned ShiftImm; member
914 unsigned ShiftImm; member
920 unsigned ShiftImm; member
3717 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,unsigned SrcReg,unsigned ShiftReg,unsigned ShiftImm,SMLoc S,SMLoc E,ARMAsmParser & Parser) CreateShiftedRegister() argument
3731 CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,unsigned SrcReg,unsigned ShiftImm,SMLoc S,SMLoc E,ARMAsmParser & Parser) CreateShiftedImmediate() argument
3888 CreateMem(unsigned BaseRegNum,const MCExpr * OffsetImm,unsigned OffsetRegNum,ARM_AM::ShiftOpc ShiftType,unsigned ShiftImm,unsigned Alignment,bool isNegative,SMLoc S,SMLoc E,ARMAsmParser & Parser,SMLoc AlignmentLoc=SMLoc ()) CreateMem() argument
3907 CreatePostIdxReg(unsigned RegNum,bool isAdd,ARM_AM::ShiftOpc ShiftTy,unsigned ShiftImm,SMLoc S,SMLoc E,ARMAsmParser & Parser) CreatePostIdxReg() argument
5685 unsigned ShiftImm = 0; parsePostIdxReg() local
6091 unsigned ShiftImm = 0; parseMemory() local
[all...] |
| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCMIPeephole.cpp | 849 unsigned ShiftImm = DefMI->getOperand(3).getImm(); simplifyCode() local
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| /llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCCodeEmitter.cpp | 941 unsigned Size, ShiftImm; getMVEShiftImmOpValue() local
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| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 2783 unsigned ShiftImm; SelectShift() local
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| /llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 1855 std::optional<int64_t> ShiftImm = getVectorShiftImm(Reg, MRI); getVectorSHLImm() local
2400 int64_t ShiftImm; earlySelect() local
[all...] |
| /llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 4509 int64_t ShiftImm; matchBitfieldExtractFromSExtInReg() local
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| /llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAG.cpp | 7036 const APInt &ShiftImm = N2C->getAPIntValue(); getNode() local
|