Lines Matching defs:ShiftImm

892     unsigned ShiftImm;        // shift for OffsetReg.
902     unsigned ShiftImm;
914     unsigned ShiftImm;
920     unsigned ShiftImm;
1723         Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1742     if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1921         (Memory.ShiftType != ARM_AM::uxtw || Memory.ShiftImm != shift))
2612       ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
2621     unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
3026                             Memory.ShiftImm, Memory.ShiftType);
3268                         Memory.ShiftImm, Memory.ShiftType);
3278     Inst.addOperand(MCOperand::createImm(Memory.ShiftImm));
3363     unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
3718                         MCRegister ShiftReg, unsigned ShiftImm, SMLoc S,
3724     Op->RegShiftedReg.ShiftImm = ShiftImm;
3732                          unsigned ShiftImm, SMLoc S, SMLoc E,
3737     Op->RegShiftedImm.ShiftImm = ShiftImm;
3893             ARM_AM::ShiftOpc ShiftType, unsigned ShiftImm, unsigned Alignment,
3901     Op->Memory.ShiftImm = ShiftImm;
3912                    unsigned ShiftImm, SMLoc S, SMLoc E, ARMAsmParser &Parser) {
3917     Op->PostIdxReg.ShiftImm = ShiftImm;
4049       OS << " shift-imm:" << Memory.ShiftImm;
4060          << PostIdxReg.ShiftImm;
4087        << RegShiftedImm.ShiftImm << ">";
5713   unsigned ShiftImm = 0;
5716     if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
5724       ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy, ShiftImm, S, E, *this));
6119   unsigned ShiftImm = 0;
6122     if (parseMemRegOffsetShift(ShiftType, ShiftImm))
6133                                            ShiftType, ShiftImm, 0, isNegative,