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Searched defs:ShiftAmount (Results 1 – 25 of 31) sorted by relevance

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/llvm-project/llvm/include/llvm/Support/
H A DDivisionByConstantInfo.h24 unsigned ShiftAmount; ///< shift amount member
/llvm-project/llvm/lib/Target/AVR/
H A DAVRShiftExpand.cpp94 Value *ShiftAmount = Builder.CreateTrunc(BI->getOperand(1), Int8Ty); in expand() local
H A DAVRISelLowering.cpp301 SDValue Cnt = DAG.getTargetConstant(ShiftAmount, dl, MVT::i8); in LowerShifts() local
369 uint64_t ShiftAmount = N->getConstantOperandVal(1); LowerShifts() local
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/llvm-project/llvm/lib/Target/SPIRV/MCTargetDesc/
H A DSPIRVBaseInfo.h261 for (unsigned ShiftAmount = 0; ShiftAmount < 32; ShiftAmount += 8) { getSPIRVStringOperand() local
/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInsertSingleUseVDST.cpp
/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMatInt.cpp109 int ShiftAmount = 0; in generateInstSeqImpl() local
/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.cpp350 uint32_t ShiftAmount = Log2_32(LMUL); lowerVSPILL() local
427 uint32_t ShiftAmount = Log2_32(LMUL); lowerVRELOAD() local
H A DRISCVInstrInfo.cpp3654 uint32_t ShiftAmount = Log2_32(Amount); mulImm() local
3667 uint32_t ShiftAmount; mulImm() local
3691 uint32_t ShiftAmount = Log2_32(Amount - 1); mulImm() local
3702 uint32_t ShiftAmount = Log2_32(Amount + 1); mulImm() local
3721 for (uint32_t ShiftAmount = 0; Amount >> ShiftAmount; ShiftAmount++) { mulImm() local
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H A DRISCVFrameLowering.cpp732 unsigned ShiftAmount = Log2(MaxAlignment); emitPrologue() local
/llvm-project/clang/lib/AST/Interp/
H A DIntegralAP.h
/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYFrameLowering.cpp177 unsigned ShiftAmount = Log2(MaxAlignment); in emitPrologue() local
/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelDAGToDAG.cpp283 selectAddrFrameIndexOffset(SDValue Addr,SDValue & Base,SDValue & Offset,unsigned OffsetBits,unsigned ShiftAmount=0) const selectAddrFrameIndexOffset() argument
/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp437 unsigned ShiftAmount; global() member
2266 CreateReg(unsigned RegNum,RegKind Kind,SMLoc S,SMLoc E,MCContext & Ctx,RegConstraintEqualityTy EqTy=RegConstraintEqualityTy::EqualsReg,AArch64_AM::ShiftExtendType ExtTy=AArch64_AM::LSL,unsigned ShiftAmount=0,unsigned HasExplicitAmount=false) CreateReg() argument
2285 CreateVectorReg(unsigned RegNum,RegKind Kind,unsigned ElementWidth,SMLoc S,SMLoc E,MCContext & Ctx,AArch64_AM::ShiftExtendType ExtTy=AArch64_AM::LSL,unsigned ShiftAmount=0,unsigned HasExplicitAmount=false) CreateVectorReg() argument
2371 CreateShiftedImm(const MCExpr * Val,unsigned ShiftAmount,SMLoc S,SMLoc E,MCContext & Ctx) CreateShiftedImm() argument
3403 int64_t ShiftAmount = getTok().getIntVal(); tryParseImmWithOptionalShift() local
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/llvm-project/llvm/lib/Analysis/
H A DValueTracking.cpp7041 shiftAmountKnownInRange(const Value * ShiftAmount) shiftAmountKnownInRange() argument
9205 unsigned ShiftAmount = Width - 1; setLimitsForBinOp() local
9226 unsigned ShiftAmount = Width - 1; setLimitsForBinOp() local
9243 unsigned ShiftAmount = C->countl_one() - 1; setLimitsForBinOp() local
9248 unsigned ShiftAmount = C->countl_zero() - 1; setLimitsForBinOp() local
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/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp2322 unsigned ShiftAmount = NLZ > NTZ ? NLZ - NTZ : NTZ - NLZ; SimplifyDemandedBits() local
7557 unsigned ShiftAmount = OuterBitSize - InnerBitSize; expandMUL_LOHI() local
9596 SDValue ShiftAmount = DAG.getShiftAmountConstant( scalarizeVectorLoad() local
9680 SDValue ShiftAmount = scalarizeVectorStore() local
9857 SDValue ShiftAmount = DAG.getShiftAmountConstant(NumBits, VT, dl); expandUnalignedLoad() local
9969 SDValue ShiftAmount = expandUnalignedStore() local
11215 int ShiftAmount = BitSize - ResultVT.getScalarSizeInBits(); expandRoundInexactToOdd() local
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H A DLegalizeVectorOps.cpp1260 SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, DL, VT); ExpandSIGN_EXTEND_VECTOR_INREG() local
H A DLegalizeIntegerTypes.cpp1083 SDValue ShiftAmount = PromoteIntRes_ADDSUBSHLSAT() local
4307 SDValue ShiftAmount = DAG.getShiftAmountConstant(Scale % NVTSize, NVT, dl); ExpandIntRes_MULFIX() local
H A DLegalizeDAG.cpp1665 int ShiftAmount = SignAsInt.SignBit - MagAsInt.SignBit; ExpandFCOPYSIGN() local
/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp968 uint64_t ShiftAmount = N->getConstantOperandVal(1); in LowerShifts() local
/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp274 emitDSLL(unsigned DstReg,unsigned SrcReg,int16_t ShiftAmount,SMLoc IDLoc,const MCSubtargetInfo * STI) emitDSLL() argument
/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp1730 shiftAmountKnownInRange(Register ShiftAmount,const MachineRegisterInfo & MRI) shiftAmountKnownInRange() argument
/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp2008 uint64_t ShiftAmount = V.getConstantOperandVal(1); in factorOutPowerOf2() local
/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineCasts.cpp419 unsigned ShiftAmount = ShiftVal ? ShiftVal->getZExtValue() : 0; in foldVecTruncToExtElt() local
/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp5362 const MCExpr *ShiftAmount; parsePKHImm() local
5426 const MCExpr *ShiftAmount; parseShifterImm() local
5476 const MCExpr *ShiftAmount; parseRotImm() local
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/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp2878 unsigned ShiftAmount = BitWidth - 16; loadImmediate() local

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