| /llvm-project/llvm/lib/MC/ |
| H A D | MCRegisterInfo.cpp | 121 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; in getSubReg() local
135 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; in getSubRegIndex() local
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| /llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyCFGSort.cpp | 223 SortRegionInfo SRI(MLI, WEI); sortBlocks() local
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| H A D | WebAssemblyCFGStackify.cpp | 402 SortRegionInfo SRI(MLI, WEI); placeLoopMarker() local
472 SortRegionInfo SRI(MLI, WEI); placeTryMarker() local
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| /llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCChecker.cpp | 82 for (MCRegAliasIterator SRI(R, &RI, RI.subregs(R).empty()); SRI.isValid(); in initReg() local
148 for (MCRegAliasIterator SRI(R, &RI, RI.subregs(R).empty()); SRI.isValid(); in init() local
[all...] |
| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNSchedStrategy.cpp | 167 initCandidate(SchedCandidate & Cand,SUnit * SU,bool AtTop,const RegPressureTracker & RPTracker,const SIRegisterInfo * SRI,unsigned SGPRPressure,unsigned VGPRPressure,bool IsBottomUp) initCandidate() argument
292 const SIRegisterInfo *SRI = static_cast<const SIRegisterInfo*>(TRI); pickNodeFromQueue() local
1372 const SIRegisterInfo *SRI = static_cast<const SIRegisterInfo *>(DAG.TRI); collectRematerializableInstructions() local
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| H A D | AMDGPUMachineCFGStructurizer.cpp | |
| /llvm-project/llvm/lib/CodeGen/ |
| H A D | VirtRegMap.cpp | 323 LiveInterval::const_iterator &SRI = RangeIterPair.second; addLiveInsForSubRanges() local
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| /llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenRegisters.cpp | 328 SubRegMap::const_iterator SRI = Map.find(Comp.first); in computeSubRegs() local
1855 for (auto SRI : SRM) { normalizeWeight() local
[all...] |
| /llvm-project/llvm/utils/TableGen/ |
| H A D | RegisterInfoEmitter.cpp | 1866 OS << "\tLaneMask: " << PrintLaneMask(SRI.LaneMask) << '\n'; in debugDump() local
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| /llvm-project/llvm/utils/TableGen/Common/GlobalISel/ |
| H A D | GlobalISelMatchTable.h | 2127 SubRegIndexRenderer(unsigned InsnID,const CodeGenSubRegIndex * SRI) SubRegIndexRenderer() argument
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| /llvm-project/llvm/lib/CodeGen/LiveDebugValues/ |
| H A D | InstrRefBasedImpl.cpp | 1930 for (MCSubRegIndexIterator SRI(SrcRegNum, TRI); SRI.isValid(); ++SRI) { performCopy() local
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| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 5881 unsigned SRI; Select() local
|