Home
last modified time | relevance | path

Searched defs:Rt (Results 1 – 24 of 24) sorted by relevance

/freebsd-src/contrib/llvm-project/clang/lib/Headers/
H A Dhvx_hexagon_protos.h63 #define Q6_V_vsplat_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplatw)(Rt) argument
129 #define Q6_Q_vsetq_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP… argument
151 #define Q6_vmem_QnRIV(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nqpred_ai)(__BUILT… argument
162 #define Q6_vmem_QnRIV_nt(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_nqpred_ai)(_… argument
173 #define Q6_vmem_QRIV_nt(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_qpred_ai)(__B… argument
184 #define Q6_vmem_QRIV(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_qpred_ai)(__BUILTIN… argument
536 #define Q6_V_valign_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valignb)(Vu,Vv,Rt) argument
569 #define Q6_V_vand_QR(Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)(__BUILTIN_VECTOR_WR… argument
580 #define Q6_V_vandor_VQR(Vx,Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt_acc)(Vx,__BUIL… argument
591 #define Q6_Q_vand_VR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_W… argument
[all …]
/freebsd-src/contrib/llvm-project/compiler-rt/lib/xray/
H A Dxray_mips.cpp41 uint32_t Rt, in encodeInstruction()
47 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction()
H A Dxray_mips64.cpp42 uint32_t Rt, in encodeInstruction()
48 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction()
/freebsd-src/contrib/llvm-project/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp618 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeAddiGroupBranch() local
646 InsnType Rt = fieldFromInstruction(insn, 21, 5); in DecodePOP35GroupBranchMMR6() local
691 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeDaddiGroupBranch() local
719 InsnType Rt = fieldFromInstruction(insn, 21, 5); in DecodePOP37GroupBranchMMR6() local
760 InsnType Rt = fieldFromInstruction(insn, 21, 5); in DecodePOP65GroupBranchMMR6() local
799 InsnType Rt = fieldFromInstruction(insn, 21, 5); in DecodePOP75GroupBranchMMR6() local
843 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeBlezlGroupBranch() local
888 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeBgtzlGroupBranch() local
930 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeBgtzGroupBranch() local
979 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeBlezGroupBranch() local
[all …]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonAsmPrinter.cpp375 MCOperand &Rt = Inst.getOperand(3); HexagonProcessInstruction() local
386 MCOperand &Rt = Inst.getOperand(2); HexagonProcessInstruction() local
398 MCOperand &Rt = Inst.getOperand(2); HexagonProcessInstruction() local
595 MCOperand &Rt = Inst.getOperand(1); HexagonProcessInstruction() local
[all...]
H A DHexagonBitTracker.cpp295 uint16_t BW, bool Odd) -> BT::RegisterCell { in evaluate()
H A DHexagonISelDAGToDAGHVX.cpp816 MaskT vshuffvdd(ArrayRef<int> Vu, ArrayRef<int> Vv, unsigned Rt) { in vshuffvdd()
836 MaskT vdealvdd(ArrayRef<int> Vu, ArrayRef<int> Vv, unsigned Rt) { in vdealvdd()
2701 SDValue Rt = N->getOperand(2); in selectVAlign() local
H A DHexagonSplitDouble.cpp374 Register Rt = MI->getOperand(2).getReg(); in profit() local
H A DHexagonBitSimplify.cpp1920 matchPackhl(unsigned SelfR,const BitTracker::RegisterCell & RC,BitTracker::RegisterRef & Rs,BitTracker::RegisterRef & Rt) matchPackhl() argument
2053 BitTracker::RegisterRef Rs, Rt; genPackhl() local
[all...]
H A DHexagonInstrInfo.cpp1347 Register Rt = Op3.getReg(); expandPostRAPseudo() local
[all...]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp2045 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeAddrMode2IdxInstruction() local
2207 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeAddrMode3Instruction() local
4070 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeT2LoadShift() local
4155 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeT2LoadImm8() local
4240 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeT2LoadImm12() local
4320 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeT2LoadT() local
4359 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeT2LoadLabel() local
4600 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeT2LdStPre() local
5095 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeDoubleRegLoad() local
5118 unsigned Rt = fieldFromInstruction(Insn, 0, 4); DecodeDoubleRegStore() local
5144 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeLDRPreImm() local
5170 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeLDRPreReg() local
5198 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeSTRPreImm() local
5224 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeSTRPreReg() local
5795 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeVMOVSRR() local
5821 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeVMOVRRS() local
5878 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeT2LDRDPreInstruction() local
5915 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeT2STRDPreInstruction() local
5984 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeSwap() local
6165 unsigned Rt = fieldFromInstruction(Val, 12, 4); DecodeLDR() local
6195 unsigned Rt = fieldFromInstruction(Val, 12, 4); DecoderForMRRC2AndMCRR2() local
6252 unsigned Rt = fieldFromInstruction(Val, 12, 4); DecodeForVMRSandVMSR() local
6796 unsigned Rt = fieldFromInstruction(Insn, 0, 4); DecodeMVEVMOVQtoDReg() local
6820 unsigned Rt = fieldFromInstruction(Insn, 0, 4); DecodeMVEVMOVDRegtoQ() local
[all...]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp1148 unsigned Rt = fieldFromInstruction(insn, 0, 5); DecodeUnsignedLdStInstruction() local
1207 unsigned Rt = fieldFromInstruction(insn, 0, 5); DecodeSignedLdStInstruction() local
1405 unsigned Rt = fieldFromInstruction(insn, 0, 5); DecodeExclusiveLdStInstruction() local
1488 unsigned Rt = fieldFromInstruction(insn, 0, 5); DecodePairLdStInstruction() local
1622 unsigned Rt = fieldFromInstruction(insn, 0, 5); DecodeAuthLoadInstruction() local
1917 uint64_t Rt = fieldFromInstruction(insn, 0, 5); DecodeTestAndBranch() local
1973 unsigned Rt = fieldFromInstruction(insn, 0, 5); DecodeSyspXzrInstruction() local
2101 uint64_t Rt = fieldFromInstruction(insn, 0, 5); DecodePRFMRegInstruction() local
[all...]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCompound.cpp201 MCOperand Rs, Rt; in getCompoundInsn() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVMergeBaseOffset.cpp180 Register Rt = TailAdd.getOperand(2).getReg(); foldLargeOffset() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp3507 Register Rt = MI.getOperand(0).getReg(); getNumMicroOpsSwiftLdSt() local
3514 Register Rt = MI.getOperand(0).getReg(); getNumMicroOpsSwiftLdSt() local
3544 Register Rt = MI.getOperand(0).getReg(); getNumMicroOpsSwiftLdSt() local
3556 Register Rt = MI.getOperand(0).getReg(); getNumMicroOpsSwiftLdSt() local
3579 Register Rt = MI.getOperand(0).getReg(); getNumMicroOpsSwiftLdSt() local
3594 Register Rt = MI.getOperand(0).getReg(); getNumMicroOpsSwiftLdSt() local
3620 Register Rt = MI.getOperand(0).getReg(); getNumMicroOpsSwiftLdSt() local
3630 Register Rt = MI.getOperand(0).getReg(); getNumMicroOpsSwiftLdSt() local
3667 Register Rt = MI.getOperand(0).getReg(); getNumMicroOpsSwiftLdSt() local
[all...]
H A DThumb2SizeReduction.cpp465 Register Rt = MI->getOperand(IsStore ? 1 : 0).getReg(); in ReduceLoadStore() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp1388 MCOperand &Rt = Inst.getOperand(1); processInstruction() local
1809 MCOperand &Rt = Inst.getOperand(2); processInstruction() local
1829 MCOperand &Rt = Inst.getOperand(3); processInstruction() local
1852 MCOperand &Rt = Inst.getOperand(2); processInstruction() local
[all...]
/freebsd-src/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp927 uint32_t Rt; // the source register in EmulatePUSH() local
1043 uint32_t Rt; // the destination register in EmulatePOP() local
1774 uint32_t Rt; // the destination register EmulateLDRRtPCRelative() local
2477 uint32_t Rt; // the source register EmulateSTRRtSP() local
4428 uint32_t Rt; // the destination register EmulateLDRRtRnImm() local
5742 uint32_t Rt = ReadCoreReg(t, &success); EmulateSTRHRegister() local
10402 uint32_t Rt = EmulateSTREX() local
10494 uint32_t Rt = ReadCoreReg(t, &success); EmulateSTRBImmARM() local
10595 uint32_t Rt = ReadCoreReg(t, &success); EmulateSTRImmARM() local
11137 uint32_t Rt = ReadCoreReg(t, &success); EmulateSTRDReg() local
[all...]
/freebsd-src/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM64/
H A DEmulateInstructionARM64.cpp701 uint32_t Rt = Bits32(opcode, 4, 0); EmulateLDPSTP() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp5271 unsigned Rt = Inst.getOperand(1).getReg(); validateInstruction() local
5296 unsigned Rt = Inst.getOperand(0).getReg(); validateInstruction() local
5309 unsigned Rt = Inst.getOperand(1).getReg(); validateInstruction() local
5325 unsigned Rt = Inst.getOperand(1).getReg(); validateInstruction() local
5358 unsigned Rt = Inst.getOperand(1).getReg(); validateInstruction() local
5377 unsigned Rt = Inst.getOperand(1).getReg(); validateInstruction() local
5393 unsigned Rt = Inst.getOperand(1).getReg(); validateInstruction() local
[all...]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp3502 Register Rt = MI.getOperand(1).getReg(); emitST_F16_PSEUDO() local
3567 Register Rt = RegInfo.createVirtualRegister(RC); emitLD_F16_PSEUDO() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp7315 unsigned Rt = MRI->getEncodingValue(Reg1); ParseInstruction() local
7436 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(RtIndex).getReg()); validateLDRDSTRD() local
7674 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg()); validateInstruction() local
7687 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); validateInstruction() local
7835 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); validateInstruction() local
[all...]
/freebsd-src/contrib/llvm-project/clang/lib/CodeGen/
H A DCGOpenMPRuntimeGPU.cpp1033 auto &Rt = emitTeamsOutlinedFunction() local
H A DCGBuiltin.cpp8442 Value *Rt = Builder.CreateTruncOrBitCast(RtAndRt2, Int32Ty); EmitARMBuiltinExpr() local
8471 Value *Rt = Builder.CreateExtractValue(RtAndRt2, 1); EmitARMBuiltinExpr() local