Lines Matching defs:Rt
927 uint32_t Rt; // the source register
946 Rt = Bits32(opcode, 15, 12);
948 if (BadReg(Rt))
950 registers = (1u << Rt);
959 Rt = Bits32(opcode, 15, 12);
961 if (Rt == dwarf_sp)
963 registers = (1u << Rt);
1043 uint32_t Rt; // the destination register
1067 Rt = Bits32(opcode, 15, 12);
1070 if (Rt == 13)
1072 if (Rt == 15 && InITBlock() && !LastInITBlock())
1074 registers = (1u << Rt);
1087 Rt = Bits32(opcode, 15, 12);
1089 if (Rt == dwarf_sp)
1091 registers = (1u << Rt);
1774 uint32_t Rt; // the destination register
1782 Rt = Bits32(opcode, 10, 8);
1787 Rt = Bits32(opcode, 15, 12);
1790 if (Rt == 15 && InITBlock() && !LastInITBlock())
1808 if (Rt == 15) {
1816 if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + Rt,
2477 uint32_t Rt; // the source register
2487 Rt = Bits32(opcode, 15, 12);
2498 if (wback && ((Rn == 15) || (Rn == Rt)))
2521 GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rt);
2524 if (Rt != 15) {
2525 uint32_t reg_value = ReadCoreReg(Rt, &success);
4428 uint32_t Rt; // the destination register
4437 Rt = Bits32(opcode, 2, 0);
4448 // t = UInt(Rt); n = 13; imm32 = ZeroExtend(imm8:'00', 32);
4449 Rt = Bits32(opcode, 10, 8);
4462 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
4463 Rt = Bits32(opcode, 15, 12);
4473 if ((Rt == 15) && InITBlock() && !LastInITBlock())
4487 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
4488 Rt = Bits32(opcode, 15, 12);
4499 if ((wback && (Rn == Rt)) ||
4500 ((Rt == 15) && InITBlock() && !LastInITBlock()))
4538 // Prepare to write to the Rt register.
4548 if (Rt == 15) {
4555 if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + Rt,
4559 WriteBits32Unknown(Rt);
5142 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5:'00', 32);
5154 // t = UInt(Rt); n = 13; imm32 = ZeroExtend(imm8:'00', 32);
5170 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
5194 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
5319 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5339 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5360 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5493 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5, 32);
5509 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
5530 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
5638 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5656 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5680 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5742 uint32_t Rt = ReadCoreReg(t, &success);
5757 if (!MemUWrite(context, address, Bits32(Rt, 15, 0), 2))
6361 // t == UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
6501 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6519 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6545 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6692 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5, 32);
6705 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
6715 // if Rt == '1111' then SEE PLD;
6735 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
6745 // if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE PLD;
6833 // t = UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == '1');
6838 // if Rt == '1111' then SEE PLD;
6849 // t == UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == '1');
6923 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6939 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6953 // if Rt == '1111' then SEE PLD;
6968 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7086 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5:'0', 32);
7099 // if Rt == '1111' then SEE "Unallocated memory hints";
7101 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
7118 // if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE
7125 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
7229 // if Rt == '1111' then SEE "Unallocated memory hints";
7230 // t = UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == '1');
7245 // t == UInt(Rt); imm32 = ZeroExtend(imm4H:imm4L, 32); add = (U == '1');
7342 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7360 // if Rt == '1111' then SEE "Unallocated memory hints";
7361 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7382 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7509 // if Rt == '1111' then SEE PLI;
7511 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
7528 // if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE PLI;
7535 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
7557 // t == UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm4H:imm4L, 32);
7654 // if Rt == '1111' then SEE PLI;
7655 // t = UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == '1');
7667 // t == UInt(Rt); imm32 = ZeroExtend(imm4H:imm4L, 32); add = (U == '1');
7749 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7766 // if Rt == '1111' then SEE PLI;
7768 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7789 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7911 // if Rt == '1111' then SEE "Unallocated memory hints";
7912 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
7930 // if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE
7937 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
7956 // t == UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm4H:imm4L, 32);
8065 // if Rt == '1111' then SEE "Unallocated memory hints";
8066 // t = UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == '1');
8078 // t == UInt(Rt); imm32 = ZeroExtend(imm4H:imm4L, 32); add = (U == '1');
8175 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
8193 // if Rt == '1111' then SEE "Unallocated memory hints";
8194 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
8216 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
10340 // d = UInt(Rd); t = UInt(Rt); n = UInt(Rn); imm32 =
10359 // d = UInt(Rd); t = UInt(Rt); n = UInt(Rn); imm32 = Zeros(32); // Zero
10402 uint32_t Rt =
10407 if (!MemAWrite(context, address, Rt, addr_byte_size))
10451 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
10494 uint32_t Rt = ReadCoreReg(t, &success);
10506 if (!MemUWrite(context, address, Bits32(Rt, 7, 0), 1))
10548 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
10595 uint32_t Rt = ReadCoreReg(t, &success);
10607 if (!MemUWrite(context, address, Rt, addr_byte_size))
10656 // t = UInt(Rt); t2 = UInt(Rt2); n = UInt(Rn); imm32 =
10680 // if Rt<0> == '1' then UNPREDICTABLE;
10681 // t = UInt(Rt); t2 = t+1; n = UInt(Rn); imm32 = ZeroExtend(imm4H:imm4L,
10800 // if Rt<0> == '1' then UNPREDICTABLE;
10801 // t = UInt(Rt); t2 = t+1; n = UInt(Rn); m = UInt(Rm);
10926 // t = UInt(Rt); t2 = UInt(Rt2); n = UInt(Rn); imm32 =
10949 // if Rt<0> == '1' then UNPREDICTABLE;
10950 // t = UInt(Rt); t2 = t+1; n = UInt(Rn); imm32 = ZeroExtend(imm4H:imm4L,
11078 // if Rt<0> == '1' then UNPREDICTABLE;
11079 // t = UInt(Rt); t2 = t+1; n = UInt(Rn); m = UInt(Rm);
11137 uint32_t Rt = ReadCoreReg(t, &success);
11158 if (!MemAWrite(context, address, Rt, addr_byte_size))
12844 &EmulateInstructionARM::EmulateSTRRtSP, "str Rt, [sp, #-imm12]!"},
13060 "ldr<c> <Rt> [<Rn> {#+/-<imm12>}]"},
13063 "ldr<c> <Rt> [<Rn> +/-<Rm> {<shift>}] {!}"},
13065 &EmulateInstructionARM::EmulateLDRBLiteral, "ldrb<c> <Rt>, [...]"},
13068 "ldrb<c> <Rt>, [<Rn>,+/-<Rm>{, <shift>}]{!}"},
13070 &EmulateInstructionARM::EmulateLDRHLiteral, "ldrh<c> <Rt>, <label>"},
13073 "ldrh<c> <Rt>,[<Rn>,+/-<Rm>]{!}"},
13076 "ldrsb<c> <Rt>, [<Rn>{,#+/-<imm8>}]"},
13078 &EmulateInstructionARM::EmulateLDRSBLiteral, "ldrsb<c> <Rt> <label>"},
13081 "ldrsb<c> <Rt>,[<Rn>,+/-<Rm>]{!}"},
13084 "ldrsh<c> <Rt>,[<Rn>{,#+/-<imm8>}]"},
13086 &EmulateInstructionARM::EmulateLDRSHLiteral, "ldrsh<c> <Rt>,<label>"},
13089 "ldrsh<c> <Rt>,[<Rn>,+/-<Rm>]{!}"},
13092 "ldrd<c> <Rt>, <Rt2>, [<Rn>,#+/-<imm8>]!"},
13095 "ldrd<c> <Rt>, <Rt2>, [<Rn>, +/-<Rm>]{!}"},
13125 "str<c> <Rt> [<Rn> +/-<Rm> {<shift>}]{!}"},
13128 "strh<c> <Rt>,[<Rn>,+/-<Rm>[{!}"},
13130 &EmulateInstructionARM::EmulateSTREX, "strex<c> <Rd>, <Rt>, [<Rn>]"},
13133 "strb<c> <Rt>,[<Rn>,#+/-<imm12>]!"},
13136 "str<c> <Rt>,[<Rn>,#+/-<imm12>]!"},
13139 "strd<c> <Rt>, <Rt2>, [<Rn> #+/-<imm8>]!"},
13142 "strd<c> <Rt>, <Rt2>, [<Rn>, +/-<Rm>]{!}"},
13209 &EmulateInstructionARM::EmulateLDRRtPCRelative, "ldr <Rt>, [PC, #imm]"},
13546 &EmulateInstructionARM::EmulateLDRRtRnImm, "ldr<c> <Rt>, [<Rn>{,#imm}]"},
13548 &EmulateInstructionARM::EmulateLDRRtRnImm, "ldr<c> <Rt>, [SP{,#imm}]"},
13551 "ldr<c>.w <Rt>, [<Rn>{,#imm12}]"},
13554 "ldr<c> <Rt>, [<Rn>{,#+/-<imm8>}]{!}"},
13558 "ldr<c>.w <Rt>, [PC, +/-#imm}]"},
13560 &EmulateInstructionARM::EmulateLDRRegister, "ldr<c> <Rt>, [<Rn>, <Rm>]"},
13563 "ldr<c>.w <Rt>, [<Rn>,<Rm>{,LSL #<imm2>}]"},
13566 "ldrb<c> <Rt>,[<Rn>{,#<imm5>}]"},
13569 "ldrb<c>.w <Rt>,[<Rn>{,#<imm12>}]"},
13572 "ldrb<c> <Rt>,[<Rn>, #+/-<imm8>]{!}"},
13574 &EmulateInstructionARM::EmulateLDRBLiteral, "ldrb<c> <Rt>,[...]"},
13576 &EmulateInstructionARM::EmulateLDRBRegister, "ldrb<c> <Rt>,[<Rn>,<Rm>]"},
13579 "ldrb<c>.w <Rt>,[<Rn>,<Rm>{,LSL #imm2>}]"},
13582 "ldrh<c> <Rt>, [<Rn>{,#<imm>}]"},
13585 "ldrh<c>.w <Rt>,[<Rn>{,#<imm12>}]"},
13588 "ldrh<c> <Rt>,[<Rn>,#+/-<imm8>]{!}"},
13590 &EmulateInstructionARM::EmulateLDRHLiteral, "ldrh<c> <Rt>, <label>"},
13593 "ldrh<c> <Rt>, [<Rn>,<Rm>]"},
13596 "ldrh<c>.w <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]"},
13599 "ldrsb<c> <Rt>,[<Rn>,#<imm12>]"},
13602 "ldrsb<c> <Rt>,[<Rn>,#+/-<imm8>]"},
13604 &EmulateInstructionARM::EmulateLDRSBLiteral, "ldrsb<c> <Rt>, <label>"},
13607 "ldrsb<c> <Rt>,[<Rn>,<Rm>]"},
13610 "ldrsb<c>.w <Rt>,[<Rn>,<Rm>{,LSL #imm2>}]"},
13613 "ldrsh<c> <Rt>,[<Rn>,#<imm12>]"},
13616 "ldrsh<c> <Rt>,[<Rn>,#+/-<imm8>]"},
13618 &EmulateInstructionARM::EmulateLDRSHLiteral, "ldrsh<c> <Rt>,<label>"},
13621 "ldrsh<c> <Rt>,[<Rn>,<Rm>]"},
13624 "ldrsh<c>.w <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]"},
13627 "ldrd<c> <Rt>, <Rt2>, [<Rn>,#+/-<imm>]!"},
13654 &EmulateInstructionARM::EmulateSTRThumb, "str<c> <Rt>, [<Rn>{,#<imm>}]"},
13656 &EmulateInstructionARM::EmulateSTRThumb, "str<c> <Rt>, [SP,#<imm>]"},
13659 "str<c>.w <Rt>, [<Rn>,#<imm12>]"},
13662 "str<c> <Rt>, [<Rn>,#+/-<imm8>]"},
13664 &EmulateInstructionARM::EmulateSTRRegister, "str<c> <Rt> ,{<Rn>, <Rm>]"},
13667 "str<c>.w <Rt>, [<Rn>, <Rm> {lsl #imm2>}]"},
13670 "strb<c> <Rt>, [<Rn>, #<imm5>]"},
13673 "strb<c>.w <Rt>, [<Rn>, #<imm12>]"},
13676 "strb<c> <Rt> ,[<Rn>, #+/-<imm8>]{!}"},
13678 &EmulateInstructionARM::EmulateSTRHRegister, "strh<c> <Rt>,[<Rn>,<Rm>]"},
13681 "strh<c>.w <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]"},
13684 "strex<c> <Rd>, <Rt>, [<Rn{,#<imm>}]"},
13687 "strd<c> <Rt>, <Rt2>, [<Rn>, #+/-<imm>]!"},