Lines Matching defs:Rt
2048 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
2056 // On stores, the writeback operand precedes Rt.
2073 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
2076 // On loads, the writeback operand comes after Rt.
2107 if (writeback && (Rn == 15 || Rn == Rt))
2210 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
2219 unsigned Rt2 = Rt + 1;
2223 // For {LD,ST}RD, Rt must be even, else undefined.
2231 if (Rt & 0x1) S = MCDisassembler::SoftFail;
2243 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
2255 if (Rt == 15)
2257 if (writeback && (Rn == 15 || Rn == Rt))
2272 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
2276 if (writeback && (Rn == Rt || Rn == Rt2))
2283 if (Rt == 15)
2287 if (Rt == 15)
2291 if (!type && writeback && (Rn == 15 || Rn == Rt))
2301 if (Rt == 15)
2305 if (type && (Rt == 15 || (writeback && Rn == Rt)))
2307 if (!type && (Rt == 15 || Rm == 15))
2309 if (!type && writeback && (Rn == 15 || Rn == Rt))
2322 // On stores, the writeback operand precedes Rt.
2338 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
2347 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
2355 // On loads, the writeback operand comes after Rt.
4073 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4112 if (Rt == 15) {
4139 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4158 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4200 if (Rt == 15) {
4228 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4243 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4282 if (Rt == 15) {
4309 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4323 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4350 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4362 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4371 if (Rt == 15) {
4395 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4603 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4626 if (Rt == 15)
4646 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
5098 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5105 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
5121 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
5128 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
5131 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
5147 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5153 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
5155 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
5173 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5180 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
5183 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
5201 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5207 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
5211 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
5227 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5233 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
5237 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
5798 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5804 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
5811 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
5824 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5830 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
5833 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
5881 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5892 if (writeback && (Rn == Rt || Rn == Rt2))
5894 if (Rt == Rt2)
5897 // Rt
5898 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
5918 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5929 if (writeback && (Rn == Rt || Rn == Rt2))
5935 // Rt
5936 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
5987 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5997 if (Rt == Rn || Rn == Rt2)
6000 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
6168 unsigned Rt = fieldFromInstruction(Val, 12, 4);
6173 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
6176 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
6198 unsigned Rt = fieldFromInstruction(Val, 12, 4);
6204 if (Rt == Rt2)
6214 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm]
6215 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm]
6218 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
6226 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
6255 unsigned Rt = fieldFromInstruction(Val, 12, 4);
6258 if (Rt == 13 || Rt == 15)
6260 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
6262 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder));
6799 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
6805 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
6823 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
6833 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))