/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorTypes.cpp | 337 EVT ResVT = N->getValueType(0); ScalarizeVecRes_OverflowOp() local 1842 EVT ResVT = N->getValueType(0); SplitVecRes_OverflowOp() local 3279 EVT ResVT = N->getValueType(0); SplitVecOp_VECREDUCE() local 3298 EVT ResVT = N->getValueType(0); SplitVecOp_VECREDUCE_SEQ() local 3324 EVT ResVT = N->getValueType(0); SplitVecOp_VP_REDUCE() local 3348 EVT ResVT = N->getValueType(0); SplitVecOp_UnaryOp() local 3391 EVT ResVT = N->getValueType(0); SplitVecOp_BITCAST() local 3416 EVT ResVT = N->getValueType(0); SplitVecOp_INSERT_SUBVECTOR() local 4113 EVT ResVT = N->getValueType(0); SplitVecOp_FP_ROUND() local 4182 EVT ResVT = N->getValueType(0); SplitVecOp_CMP() local 4194 EVT ResVT = N->getValueType(0); SplitVecOp_FP_TO_XINT_SAT() local 4212 EVT ResVT = N->getValueType(0); SplitVecOp_VP_CttzElements() local 4917 EVT ResVT = N->getValueType(0); WidenVecRes_OverflowOp() local 6485 EVT ResVT = N->getValueType(0); WidenVecOp_CMP() local 6530 EVT ResVT = WidenVecOp_IS_FPCLASS() local 7038 EVT ResVT = EVT::getVectorVT(*DAG.getContext(), WidenVecOp_SETCC() local [all...] |
H A D | LegalizeIntegerTypes.cpp | 360 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); PromoteIntRes_Atomic0() local 2575 EVT ResVT = N->getValueType(0); PromoteIntOp_VECREDUCE() local 5680 EVT ResVT = V0.getValueType(); PromoteIntRes_VECTOR_INTERLEAVE_DEINTERLEAVE() local 6058 EVT ResVT = N->getValueType(0); PromoteIntOp_CONCAT_VECTORS() local [all...] |
H A D | SelectionDAG.cpp | 2057 getStepVector(const SDLoc & DL,EVT ResVT) getStepVector() argument 2062 getStepVector(const SDLoc & DL,EVT ResVT,const APInt & StepVal) getStepVector() argument 12416 EVT ResVT = N->getValueType(0); UnrollVectorOverflowOp() local [all...] |
H A D | TargetLowering.cpp | 9113 EVT ResVT = N->getValueType(0); expandVPCTTZElements() local 10378 EVT ResVT = Node->getValueType(0); expandCMP() local [all...] |
H A D | DAGCombiner.cpp | 8177 EVT ResVT = ExtractFrom.getValueType(); extractShiftForRotate() local 19402 EVT ResVT = Use->getValueType(0); canMergeExpensiveCrossRegisterBankCopy() local [all...] |
/llvm-project/llvm/lib/Target/VE/ |
H A D | VVPISelLowering.cpp | 351 MVT ResVT = splitVectorType(Op.getValue(0).getSimpleValueType()); in splitVectorOp() local
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H A D | VECustomDAG.cpp | 562 SDValue VECustomDAG::getLegalReductionOpVVP(unsigned VVPOpcode, EVT ResVT, in getLegalReductionOpVVP() argument
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/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyISelLowering.cpp | 2511 EVT ResVT = N->getValueType(0); performVectorExtendToFPCombine() local 2545 EVT ResVT = N->getValueType(0); performVectorExtendCombine() local 2614 EVT ResVT; performVectorTruncZeroCombine() local 2661 EVT ResVT; performVectorTruncZeroCombine() local [all...] |
/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMTargetTransformInfo.cpp | 1771 EVT ResVT = TLI->getValueType(DL, ResTy); getExtendedReductionCost() local 1806 EVT ResVT = TLI->getValueType(DL, ResTy); getMulAccReductionCost() local
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H A D | ARMISelLowering.cpp | 17116 EVT ResVT = N->getValueType(0); PerformVECREDUCE_ADDCombine() local 21270 isExtractSubvectorCheap(EVT ResVT,EVT SrcVT,unsigned Index) const isExtractSubvectorCheap() argument [all...] |
/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 6044 EVT ResVT = N->getValueType(0); ReplaceLoadVector() local 6204 EVT ResVT = N->getValueType(0); ReplaceINTRINSIC_W_CHAIN() local [all...] |
/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 1936 shouldExpandGetActiveLaneMask(EVT ResVT,EVT OpVT) const shouldExpandGetActiveLaneMask() argument 6019 EVT ResVT = Op.getValueType(); LowerINTRINSIC_WO_CHAIN() local 14643 canLowerSRLToRoundingShiftForVT(SDValue Shift,EVT ResVT,SelectionDAG & DAG,unsigned & ShiftValue,SDValue & RShOperand) canLowerSRLToRoundingShiftForVT() argument 17388 isExtractSubvectorCheap(EVT ResVT,EVT SrcVT,unsigned Index) const isExtractSubvectorCheap() argument 21869 EVT ResVT = N->getValueType(0); tryCombineExtendRShTrunc() local 21911 EVT ResVT; trySimplifySrlAddToRshrnb() local 21937 EVT ResVT = N->getValueType(0); performUzpCombine() local 22127 EVT ResVT = N->getValueType(0); performGLD1Combine() local 24040 EVT ResVT = N->getValueType(0); performVSelectCombine() local 24063 EVT ResVT = N->getValueType(0); performSelectCombine() local 27433 EVT ResVT = SrcVT.getVectorElementType(); LowerVECREDUCE_SEQ_FADD() local 27513 EVT ResVT = (Opcode == AArch64ISD::UADDV_PRED) ? MVT::i64 : LowerReductionToSVE() local [all...] |
/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | BasicTTIImpl.h | 1747 EVT ResVT = getTLI()->getValueType(DL, RetTy, true); getIntrinsicInstrCost() local
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H A D | TargetLowering.h | 3318 isExtractSubvectorCheap(EVT ResVT,EVT SrcVT,unsigned Index) isExtractSubvectorCheap() argument
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/llvm-project/llvm/lib/Target/X86/ |
H A D | X86FastISel.cpp | 3616 EVT ResVT = VA.getValVT(); fastLowerCall() local
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H A D | X86ISelLowering.cpp | 3200 isExtractSubvectorCheap(EVT ResVT,EVT SrcVT,unsigned Index) const isExtractSubvectorCheap() argument 9241 MVT ResVT = Op.getSimpleValueType(); LowerAVXCONCAT_VECTORS() local 9309 MVT ResVT = Op.getSimpleValueType(); LowerCONCAT_VECTORSvXi1() local 20101 EVT ResVT = getSetCCResultType(DAG.getDataLayout(), FP_TO_INTHelper() local 20905 MVT ResVT = MVT::v4i32; LowerFP_TO_INT() local 20946 MVT ResVT = VT; LowerFP_TO_INT() local 21022 MVT ResVT = SrcVT == MVT::v4f64 ? MVT::v8i32 : MVT::v16i32; LowerFP_TO_INT() local 32719 EVT ResVT = getTypeToTransformTo(*DAG.getContext(), VT); ReplaceNodeResults() local 32941 EVT ResVT = EleVT == MVT::i32 ? MVT::v4i32 : MVT::v8i16; ReplaceNodeResults() local 44498 EVT ResVT = combineVPDPBUSDPattern() local 44573 EVT ResVT = EVT::getVectorVT(*DAG.getContext(), ExtractVT, combineBasicSADPattern() local 47501 EVT ResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts / 2); reduceVMULWidth() local 47721 MVT ResVT = MVT::getVectorVT(MVT::i32, Ops[0].getValueSizeInBits() / 32); combineMulToPMADDWD() local 52478 EVT ResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i16, detectPMADDUBSW() local 55378 EVT ResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, matchPMADDWD() local 55503 EVT ResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, matchPMADDWD_2() local [all...] |
H A D | X86ISelDAGToDAG.cpp | 4957 MVT ResVT = Setcc.getSimpleValueType(); tryVPTESTM() local
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/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 3839 EVT ResVT = Op.getValueType(); lowerBITCAST() local 6531 combineExtract(const SDLoc & DL,EVT ResVT,EVT VecVT,SDValue Op,unsigned Index,DAGCombinerInfo & DCI,bool Force) const combineExtract() argument 6663 EVT ResVT = (TruncBytes < 4 ? MVT::i32 : TruncVT); combineTruncateExtract() local [all...] |
/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 2185 isExtractSubvectorCheap(EVT ResVT,EVT SrcVT,unsigned Index) const isExtractSubvectorCheap() argument
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/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 2279 isExtractSubvectorCheap(EVT ResVT,EVT SrcVT,unsigned Index) const isExtractSubvectorCheap() argument 9792 lowerReductionSeq(unsigned RVVOpcode,MVT ResVT,SDValue StartValue,SDValue Vec,SDValue Mask,SDValue VL,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerReductionSeq() argument 9925 MVT ResVT = Op.getSimpleValueType(); lowerFPVECREDUCE() local 9994 MVT ResVT = Res.getSimpleValueType(); lowerVPREDUCE() local [all...] |
/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIISelLowering.cpp | 1915 isExtractSubvectorCheap(EVT ResVT,EVT SrcVT,unsigned Index) const isExtractSubvectorCheap() argument 5741 auto ResVT = DAG.GetSplitDestVTs(VT); splitTernaryVectorOp() local 13375 EVT ResVT = N->getValueType(0); performExtractVectorEltCombine() local [all...] |
/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 4581 EVT ResVT = VecVT.changeVectorElementTypeToInteger(); in trySETCC() local
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H A D | PPCISelLowering.cpp | 8173 EVT ResVT = Op.getValueType(); LowerSELECT_CC() local 15373 EVT ResVT = Val.getValueType(); combineStoreFPToInt() local [all...] |