| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64LowerHomogeneousPrologEpilog.cpp | 131 getFrameHelperName(SmallVectorImpl<unsigned> & Regs,FrameHelperType Type,unsigned FpOffset) getFrameHelperName() argument
313 getOrCreateFrameHelper(Module * M,MachineModuleInfo * MMI,SmallVectorImpl<unsigned> & Regs,FrameHelperType Type,unsigned FpOffset=0) getOrCreateFrameHelper() argument
396 shouldUseFrameHelper(MachineBasicBlock & MBB,MachineBasicBlock::iterator & NextMBBI,SmallVectorImpl<unsigned> & Regs,FrameHelperType Type) shouldUseFrameHelper() argument
474 SmallVector<unsigned, 8> Regs; lowerEpilog() local
557 SmallVector<unsigned, 8> Regs; lowerProlog() local
[all...] |
| H A D | AArch64ISelDAGToDAG.cpp | 1373 createDTuple(ArrayRef<SDValue> Regs) createDTuple() argument
1382 createQTuple(ArrayRef<SDValue> Regs) createQTuple() argument
1391 createZTuple(ArrayRef<SDValue> Regs) createZTuple() argument
1401 createZMulTuple(ArrayRef<SDValue> Regs) createZMulTuple() argument
1413 createTuple(ArrayRef<SDValue> Regs,const unsigned RegClassIDs[],const unsigned SubRegs[]) createTuple() argument
1451 SmallVector<SDValue, 4> Regs(N->op_begin() + Vec0Off, SelectTable() local
1746 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); SelectCVTIntrinsic() local
1770 SmallVector<SDValue, 4> Regs(N->op_begin() + StartIdx, SelectDestructiveMultiIntrinsic() local
1905 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); SelectClamp() local
1995 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, SelectUnaryMultiIntrinsic() local
2020 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); SelectStore() local
2039 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); SelectPredicatedStore() local
2084 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); SelectPostStore() local
2138 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); SelectLoadLane() local
2176 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); SelectPostLoadLane() local
2230 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); SelectStoreLane() local
2258 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); SelectPostStoreLane() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZRegisterInfo.cpp | 243 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); in getCalleeSavedRegs() local
253 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); in getCallPreservedMask() local
262 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); in getReservedRegs() local
435 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); in getFrameRegister() local
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| H A D | SystemZFrameLowering.cpp | 923 auto *Regs = isXPLeafCandidate() local
972 auto &Regs = Subtarget.getSpecialRegisters<SystemZXPLINK64Registers>(); assignCalleeSavedSpillSlots() local
1069 auto &Regs = Subtarget.getSpecialRegisters<SystemZXPLINK64Registers>(); determineCalleeSaves() local
1087 auto &Regs = Subtarget.getSpecialRegisters<SystemZXPLINK64Registers>(); spillCalleeSavedRegisters() local
1149 auto &Regs = Subtarget.getSpecialRegisters<SystemZXPLINK64Registers>(); restoreCalleeSavedRegisters() local
1206 auto &Regs = Subtarget.getSpecialRegisters<SystemZXPLINK64Registers>(); emitPrologue() local
1321 auto &Regs = Subtarget.getSpecialRegisters<SystemZXPLINK64Registers>(); emitEpilogue() local
1458 auto &Regs = Subtarget.getSpecialRegisters<SystemZXPLINK64Registers>(); processFunctionBeforeFrameFinalized() local
1481 auto *Regs = determineFrameLayout() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | CallingConvLower.h | 315 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { in getFirstUnallocated()
349 MCPhysReg AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg()
363 MCPhysReg AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) { in AllocateRegBlock()
390 MCRegister AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) { in AllocateReg()
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| H A D | RegisterPressure.h | 276 RegSet Regs; variable
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| H A D | RDFRegisters.h | 193 BitVector Regs; member
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| /freebsd-src/contrib/llvm-project/llvm/include/llvm/MCA/ |
| H A D | HWEventListener.h | 78 HWInstructionDispatchedEvent(const InstRef &IR, ArrayRef<unsigned> Regs, in HWInstructionDispatchedEvent()
99 HWInstructionRetiredEvent(const InstRef &IR, ArrayRef<unsigned> Regs) in HWInstructionRetiredEvent()
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| /freebsd-src/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | RegisterInfoEmitter.cpp | 219 const CodeGenRegister::Vec &Regs = RC.getMembers(); EmitRegUnitPressure() local
384 EmitRegMappingTables(raw_ostream & OS,const std::deque<CodeGenRegister> & Regs,bool isCtor) EmitRegMappingTables() argument
511 EmitRegMapping(raw_ostream & OS,const std::deque<CodeGenRegister> & Regs,bool isCtor) EmitRegMapping() argument
878 const auto &Regs = RegBank.getRegisters(); runMCDesc() local
1442 const auto &Regs = RegBank.getRegisters(); runTargetDesc() local
1679 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); runTargetDesc() local
[all...] |
| H A D | CodeGenRegisters.cpp | |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyRegisterInfo.cpp | 145 static const unsigned Regs[2][2] = { in getFrameRegister() local
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| /freebsd-src/contrib/llvm-project/clang/lib/StaticAnalyzer/Checkers/ |
| H A D | Taint.cpp | 139 TaintedSubRegions Regs = SavedRegs ? *SavedRegs : F.getEmptyMap(); addPartialTaint() local
283 if (const TaintedSubRegions *Regs = getTaintedSymbolsImpl() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | Thumb2ITBlockPass.cpp | 99 auto InsertUsesDefs = [&](RegList &Regs, RegisterSet &UsesDefs) { in INITIALIZE_PASS() argument
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| H A D | ARMLoadStoreOptimizer.cpp | 616 ContainsReg(const ArrayRef<std::pair<unsigned,bool>> & Regs,unsigned Reg) ContainsReg() argument
631 CreateLoadStoreMulti(MachineBasicBlock & MBB,MachineBasicBlock::iterator InsertBefore,int Offset,unsigned Base,bool BaseKill,unsigned Opcode,ARMCC::CondCodes Pred,unsigned PredReg,const DebugLoc & DL,ArrayRef<std::pair<unsigned,bool>> Regs,ArrayRef<MachineInstr * > Instrs) CreateLoadStoreMulti() argument
838 CreateLoadStoreDouble(MachineBasicBlock & MBB,MachineBasicBlock::iterator InsertBefore,int Offset,unsigned Base,bool BaseKill,unsigned Opcode,ARMCC::CondCodes Pred,unsigned PredReg,const DebugLoc & DL,ArrayRef<std::pair<unsigned,bool>> Regs,ArrayRef<MachineInstr * > Instrs) const CreateLoadStoreDouble() argument
864 SmallVector<std::pair<unsigned, bool>, 8> Regs; MergeOpsUpdate() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUPALMetadata.cpp | 160 auto Regs = getRegisters(); getRegister() local
671 auto Regs = getRegisters(); toString() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SILoadStoreOptimizer.cpp | 777 AddressRegs Regs = getRegs(Opc, *LSO.TII); setMI() local
1466 AddressRegs Regs = getRegs(Opcode, *TII); mergeBufferLoadPair() local
1521 AddressRegs Regs = getRegs(Opcode, *TII); mergeTBufferLoadPair() local
1592 AddressRegs Regs = getRegs(Opcode, *TII); mergeTBufferStorePair() local
1921 AddressRegs Regs = getRegs(Opcode, *TII); mergeBufferStorePair() local
[all...] |
| H A D | AMDGPUArgumentUsageInfo.h | 97 SmallVector<MCRegister> Regs; member
|
| /freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | AggressiveAntiDepBreaker.cpp | 80 std::vector<unsigned> &Regs, in GetGroupRegs() argument
546 std::vector<unsigned> Regs; in FindSuitableFreeRegisters() local
[all...] |
| H A D | ExecutionDomainFix.cpp | 329 SmallVector<int, 4> Regs; in visitSoftInstr() local
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| H A D | CallingConvLower.cpp | 201 void CCState::getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs, in getRemainingRegParmsForType()
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| H A D | RDFRegisters.cpp | 367 BitVector Regs = PRI.getUnitAliases(U); in makeRegRef() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | InlineAsmLowering.cpp | 35 SmallVector<Register, 1> Regs; member in __anon51a38c3a0111::GISelAsmOperandInfo
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 240 createTuple(SelectionDAG & CurDAG,ArrayRef<SDValue> Regs,unsigned NF,RISCVII::VLMUL LMUL) createTuple() argument
351 SmallVector<SDValue, 8> Regs(Node->op_begin() + CurOp, selectVLSEG() local
391 SmallVector<SDValue, 8> Regs(Node->op_begin() + CurOp, selectVLSEGFF() local
433 SmallVector<SDValue, 8> Regs(Node->op_begin() + CurOp, selectVLXSEG() local
484 SmallVector<SDValue, 8> Regs(Node->op_begin() + 2, Node->op_begin() + 2 + NF); selectVSSEG() local
514 SmallVector<SDValue, 8> Regs(Node->op_begin() + 2, Node->op_begin() + 2 + NF); selectVSXSEG() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | CallLowering.h | 63 SmallVector<Register, 4> Regs; member
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYFrameLowering.cpp | 412 const MCPhysReg *Regs = MF.getRegInfo().getCalleeSavedRegs(); in determineCalleeSaves() local
|