Lines Matching defs:Regs

88   void EmitRegMapping(raw_ostream &o, const std::deque<CodeGenRegister> &Regs,
91                             const std::deque<CodeGenRegister> &Regs,
218     const CodeGenRegister::Vec &Regs = RC.getMembers();
220     if (Regs.empty() || RC.Artificial)
381     raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) {
387   for (auto &RE : Regs) {
403   StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace");
448   for (auto &RE : Regs) {
508     raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) {
512   for (auto &RE : Regs) {
521   StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace");
872   const auto &Regs = RegBank.getRegisters();
881   SmallVector<DiffVec, 4> SubRegLists(Regs.size());
882   SmallVector<DiffVec, 4> SuperRegLists(Regs.size());
883   SmallVector<DiffVec, 4> RegUnitLists(Regs.size());
887   SmallVector<MaskVec, 4> RegUnitLaneMasks(Regs.size());
893   SmallVector<SubRegIdxVec, 4> SubRegIdxLists(Regs.size());
899   for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I, ++i) {
968   for (const auto &Reg : Regs) {
1063   EmitRegMappingTables(OS, Regs, false);
1070   for (const auto &RE : Regs) {
1088      << Regs.size() + 1 << ", RA, PC, " << TargetName << "MCRegisterClasses, "
1096   EmitRegMapping(OS, Regs, false);
1440   const auto &Regs = RegBank.getRegisters();
1442   for (const auto &Reg : Regs)
1446   llvm::BitVector InAllocClass(Regs.size() + 1, false);
1452   for (const auto &Reg : Regs) {
1465   // Size of the emitted array should be NumRegCosts * (Regs.size() + 1).
1606       OS << "  static const uint16_t Mapping[" << Regs.size() + 1 << "] = {\n";
1608       for (const CodeGenRegister &Reg : Regs) {
1641   EmitRegMappingTables(OS, Regs, true);
1654      << "  InitMCRegisterInfo(" << TargetName << "RegDesc, " << Regs.size() + 1
1667   EmitRegMapping(OS, Regs, true);
1676     const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet);
1677     assert(Regs && "Cannot expand CalleeSavedRegs instance");
1681     for (unsigned r = 0, re = Regs->size(); r != re; ++r)
1682       OS << getQualifiedName((*Regs)[r]) << ", ";
1686     BitVector Covered = RegBank.computeCoveredRegisters(*Regs);
1773   for (const auto &Reg : Regs)