| /llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AddressingModes.h | 831 inline static bool isAnyMOVZMovAlias(uint64_t Value, int RegWidth) { in isAnyMOVZMovAlias()
839 inline static bool isMOVZMovAlias(uint64_t Value, int Shift, int RegWidth) { in isMOVZMovAlias()
850 inline static bool isMOVNMovAlias(uint64_t Value, int Shift, int RegWidth) { in isMOVNMovAlias()
862 inline static bool isAnyMOVWMovAlias(uint64_t Value, int RegWidth) { in isAnyMOVWMovAlias()
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| H A D | AArch64InstPrinter.cpp | 300 int64_t SExtVal = SignExtend64(Value, RegWidth); in printInst() argument
324 int RegWidth = Opcode == AArch64::MOVZXi ? 64 : 32; printInst() local
337 int RegWidth = Opcode == AArch64::MOVNXi ? 64 : 32; printInst() local
353 int RegWidth = Opcode == AArch64::ORRXri ? 64 : 32; printInst() local
[all...] |
| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonTargetTransformInfo.cpp | 183 unsigned RegWidth = in getMemoryOpCost() local
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| /llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 1283 usesRegister(RegisterKind RegKind,unsigned DwordRegIndex,unsigned RegWidth) usesRegister() argument
2493 getRegClass(RegisterKind Is,unsigned RegWidth) getRegClass() argument
2678 AddNextRegisterToList(unsigned & Reg,unsigned & RegWidth,RegisterKind RegKind,unsigned Reg1,SMLoc Loc) AddNextRegisterToList() argument
2803 getRegularReg(RegisterKind RegKind,unsigned RegNum,unsigned SubReg,unsigned RegWidth,SMLoc Loc) getRegularReg() argument
2846 ParseRegRange(unsigned & Num,unsigned & RegWidth) ParseRegRange() argument
2889 ParseSpecialReg(RegisterKind & RegKind,unsigned & RegNum,unsigned & RegWidth,SmallVectorImpl<AsmToken> & Tokens) ParseSpecialReg() argument
2904 ParseRegularReg(RegisterKind & RegKind,unsigned & RegNum,unsigned & RegWidth,SmallVectorImpl<AsmToken> & Tokens) ParseRegularReg() argument
2948 ParseRegList(RegisterKind & RegKind,unsigned & RegNum,unsigned & RegWidth,SmallVectorImpl<AsmToken> & Tokens) ParseRegList() argument
3002 ParseAMDGPURegister(RegisterKind & RegKind,unsigned & Reg,unsigned & RegNum,unsigned & RegWidth,SmallVectorImpl<AsmToken> & Tokens) ParseAMDGPURegister() argument
3034 ParseAMDGPURegister(RegisterKind & RegKind,unsigned & Reg,unsigned & RegNum,unsigned & RegWidth,bool RestoreOnFailure) ParseAMDGPURegister() argument
3071 updateGprCountSymbols(RegisterKind RegKind,unsigned DwordRegIndex,unsigned RegWidth) updateGprCountSymbols() argument
3104 unsigned Reg, RegNum, RegWidth; parseRegister() local
[all...] |
| /llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVTargetTransformInfo.cpp | 1900 TypeSize RegWidth = getMaximumVF() local
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| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 3762 checkCVTFixedPointOperandWithFBits(SelectionDAG * CurDAG,SDValue N,SDValue & FixedPos,unsigned RegWidth,bool isReciprocal) checkCVTFixedPointOperandWithFBits() argument
3811 SelectCVTFixedPosOperand(SDValue N,SDValue & FixedPos,unsigned RegWidth) SelectCVTFixedPosOperand() argument
3818 SelectCVTFixedPosRecipOperand(SDValue N,SDValue & FixedPos,unsigned RegWidth) SelectCVTFixedPosRecipOperand() argument
[all...] |
| /llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 6262 uint64_t RegWidth = 0; MatchAndEmitInstruction() local
6318 uint64_t RegWidth = 0; MatchAndEmitInstruction() local
6382 uint64_t RegWidth = 0; MatchAndEmitInstruction() local
[all...] |
| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 1352 const unsigned RegWidth = AMDGPU::getRegBitWidth(*RC) / 8; buildSpillLoadStore() local
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| /llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 1760 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits(); global() variable
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| /llvm-project/llvm/lib/CodeGen/ |
| H A D | CodeGenPrepare.cpp | 7428 unsigned RegWidth = RegType.getSizeInBits(); optimizeSwitchType() local
|