Lines Matching defs:RegWidth

1300                     unsigned RegWidth) {
1303       usesSgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1);
1306       usesAgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1);
1309       usesVgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1);
1380   bool AddNextRegisterToList(MCRegister &Reg, unsigned &RegWidth,
1383                            unsigned &RegNum, unsigned &RegWidth,
1386                            unsigned &RegNum, unsigned &RegWidth,
1389                              unsigned &RegWidth,
1392                              unsigned &RegWidth,
1395                           unsigned &RegWidth,
1399                            unsigned SubReg, unsigned RegWidth, SMLoc Loc);
1406                              unsigned RegWidth);
2533 static int getRegClass(RegisterKind Is, unsigned RegWidth) {
2535     switch (RegWidth) {
2567     switch (RegWidth) {
2581     switch (RegWidth) {
2611     switch (RegWidth) {
2718 bool AMDGPUAsmParser::AddNextRegisterToList(MCRegister &Reg, unsigned &RegWidth,
2725       RegWidth = 64;
2730       RegWidth = 64;
2735       RegWidth = 64;
2740       RegWidth = 64;
2745       RegWidth = 64;
2750       RegWidth = 64;
2759     if (Reg1 != Reg + RegWidth / 32) {
2763     RegWidth += 32;
2843                                           unsigned SubReg, unsigned RegWidth,
2851     AlignSize = std::min(llvm::bit_ceil(RegWidth / 32), 4u);
2860   int RCID = getRegClass(RegKind, RegWidth);
2886 bool AMDGPUAsmParser::ParseRegRange(unsigned &Num, unsigned &RegWidth) {
2924   RegWidth = 32 * ((RegHi - RegLo) + 1);
2930                                             unsigned &RegWidth,
2936     RegWidth = 32;
2946                                             unsigned &RegWidth,
2975     RegWidth = 32;
2978     if (!ParseRegRange(RegNum, RegWidth))
2982   return getRegularReg(RegKind, RegNum, SubReg, RegWidth, Loc);
2986                                          unsigned &RegNum, unsigned &RegWidth,
2999   if (!ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth))
3001   if (RegWidth != 32) {
3025     if (!AddNextRegisterToList(Reg, RegWidth, RegKind, NextReg, Loc))
3035     Reg = getRegularReg(RegKind, RegNum, NoSubRegister, RegWidth, ListLoc);
3042                                           unsigned &RegWidth,
3048     Reg = ParseSpecialReg(RegKind, RegNum, RegWidth, Tokens);
3050       Reg = ParseRegularReg(RegKind, RegNum, RegWidth, Tokens);
3052     Reg = ParseRegList(RegKind, RegNum, RegWidth, Tokens);
3076                                           unsigned &RegWidth,
3081   if (ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth, Tokens)) {
3113                                             unsigned RegWidth) {
3123   int64_t NewMax = DwordRegIndex + divideCeil(RegWidth, 32) - 1;
3147   unsigned RegNum, RegWidth;
3149   if (!ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth)) {
3153     if (!updateGprCountSymbols(RegKind, RegNum, RegWidth))
3156     KernelScope.usesRegister(RegKind, RegNum, RegWidth);