| /llvm-project/llvm/lib/CodeGen/ |
| H A D | RegisterUsageInfo.cpp | 58 storeUpdateRegUsageInfo(const Function & FP,ArrayRef<uint32_t> RegMask) storeUpdateRegUsageInfo() argument
76 for (const auto &RegMask : RegMasks) print() local
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| H A D | RegUsageInfoPropagate.cpp | 61 MO.setRegMask(RegMask.data()); in setRegMask() argument
122 const ArrayRef<uint32_t> RegMask = PRUI->getRegUsageInfo(F); runOnMachineFunction() local
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| H A D | LiveRegUnits.cpp | 22 void LiveRegUnits::removeRegsNotPreserved(const uint32_t *RegMask) { in removeRegsNotPreserved()
33 void LiveRegUnits::addRegsInMask(const uint32_t *RegMask) { in addRegsInMask()
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| H A D | MachineStableHash.cpp | 126 const uint32_t *RegMask = MO.getRegMask(); stableHashValue() local
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| H A D | RegUsageInfoCollector.cpp | 122 std::vector<uint32_t> RegMask; runOnMachineFunction() local
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| H A D | MachineOperand.cpp | 354 const uint32_t *RegMask = getRegMask(); in isIdenticalTo() local
424 const uint32_t *RegMask = MO.getRegMask(); hash_value() local
958 const uint32_t *RegMask = getRegLiveOut(); print() local
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| H A D | MIRPrinter.cpp | 268 printCustomRegMask(const uint32_t * RegMask,raw_ostream & OS,const TargetRegisterInfo * TRI) printCustomRegMask() argument
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| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64CollectLOH.cpp | 486 if (!MachineOperand::clobbersPhysReg(RegMask, Reg)) in handleRegMaskClobber() argument
499 handleRegMaskClobber(RegMask, Reg, LOHInfos); in handleNormalInst() local
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| /llvm-project/llvm/unittests/ExecutionEngine/JITLink/ |
| H A D | AArch32Tests.cpp | 241 constexpr HalfWords RegMask = FixupInfo<Thumb_MovtAbs>::RegMask; in TEST() local
281 constexpr uint32_t RegMask = FixupInfo<Arm_MovtAbs>::RegMask; in TEST() local
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| /llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kRegisterInfo.cpp | 153 const uint32_t *RegMask = getCallPreservedMask(MF, CC); in getReservedRegs() local
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| H A D | M68kFrameLowering.cpp | 178 __anoncf9062860102(MachineBasicBlock::RegisterMaskPair RegMask) isRegLiveIn() argument
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| /llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineOperand.h | 174 const uint32_t *RegMask; // For MO_RegisterMask and MO_RegisterLiveOut. member
646 static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg) { in clobbersPhysReg() argument
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| H A D | MachineRegisterInfo.h | 903 addPhysRegsUsedFromRegMask(const uint32_t * RegMask) addPhysRegsUsedFromRegMask() argument
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| /llvm-project/llvm/lib/Target/M68k/AsmParser/ |
| H A D | M68kAsmParser.cpp | 83 RegMask, enumerator
111 uint16_t RegMask; member
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| /llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZElimCompare.cpp | 631 RegMask = MBBI->getOperand(3).getRegMask(); in fuseCompareOperations() local
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| H A D | SystemZInstrInfo.cpp | 830 const uint32_t *RegMask = MI.getOperand(1).getRegMask(); in PredicateInstruction() local
844 const uint32_t *RegMask = MI.getOperand(1).getRegMask(); in PredicateInstruction() local
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| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ExpandPseudo.cpp | 238 const uint32_t *RegMask = expandCALL_RVMARKER() local
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| H A D | X86RegisterInfo.cpp | 569 const uint32_t *RegMask = getCallPreservedMask(MF, CC); getReservedRegs() local
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| /llvm-project/llvm/tools/llvm-reduce/ |
| H A D | ReducerWorkItem.cpp | 335 if (auto *RegMask = TRI->getCustomEHPadPreservedMask(*DstMF)) cloneMF() local
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| /llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGRRList.cpp | 1321 static void CheckForLiveRegDefMasked(SUnit *SU, const uint32_t *RegMask, in CheckForLiveRegDefMasked() argument
1417 if (const uint32_t *RegMask = getNodeRegMask(Node)) in DelayForLiveRegsBottomUp() local
2862 const uint32_t *RegMask = getNodeRegMask(SU->getNode()); in canClobberReachingPhysRegUse() local
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| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNRegPressure.cpp | 620 LaneBitmask RegMask = MRI.getMaxLaneMaskForVReg(Reg); getRegLiveThroughMask() local
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| /llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCCodeEmitter.cpp | 606 unsigned RegMask = MI.getOperand(OpIdx).getImm(); EncodeMatrixTileListRegisterClass() local
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| /llvm-project/llvm/lib/CodeGen/MIRParser/ |
| H A D | MIRParser.cpp | 743 if (auto *RegMask = TRI->getCustomEHPadPreservedMask(MF)) setupRegisterInfo() local
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| /llvm-project/llvm/lib/Analysis/ |
| H A D | VectorUtils.cpp | 539 SmallVectorImpl<int> &RegMask = Dest[I]; processShuffleMasks() local
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| /llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 415 unsigned RegMask = 0; global() member
1906 unsigned RegMask = getMatrixTileListRegMask(); addMatrixTileListOperands() local
2323 CreateMatrixTileList(unsigned RegMask,SMLoc S,SMLoc E,MCContext & Ctx) CreateMatrixTileList() argument
2603 unsigned RegMask = getMatrixTileListRegMask(); print() local
4460 unsigned RegMask = 0; tryParseMatrixTileList() local
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