LiveRegUnits: Break register loop when a clobber is encountered

LiveRegUnits: Cleanup isReg checks

This is the common case and should be checked first. Provides a very
marginal compile time improvement on the example I'm looking at.

LiveRegUnits: Do not use phys_regs_and_masks

Somehow DeadMachineInstructionElim is about 3x slower when using it.
Hopefully this reverses the compile time regression reported for
b5041527c75de2f409a

LiveRegUnits: Do not use phys_regs_and_masks

Somehow DeadMachineInstructionElim is about 3x slower when using it.
Hopefully this reverses the compile time regression reported for
b5041527c75de2f409aa9e2e6deba12b17834c59.

show more ...

[ARM][RegisterScavenging] Don't consider LR liveout if it is not reloaded

https://bugs.llvm.org/show_bug.cgi?id=48232

When PrologEpilogInserter writes callee-saved registers to the stack, LR is not

[ARM][RegisterScavenging] Don't consider LR liveout if it is not reloaded

https://bugs.llvm.org/show_bug.cgi?id=48232

When PrologEpilogInserter writes callee-saved registers to the stack, LR is not reloaded but is instead loaded directly into PC.
This was not taken into account when determining if each callee-saved register was liveout for the block.
When frame elimination inserts virtual registers, and the register scavenger tries to scavenge LR, it considers it liveout and tries to spill again.
However there is no emergency spill slot to use, and it fails with an error:

fatal error: error in backend: Error while trying to spill LR from class GPR: Cannot scavenge register without an emergency spill slot!

This patch pervents any callee-saved registers which are not reloaded (including LR) from being marked liveout.
They are therefore available to scavenge without requiring an extra spill.

show more ...

LiveRegUnits.h - reduce MachineRegisterInfo.h include. NFC.

We only need to include MachineInstrBundle.h, but exposes an implicit dependency in MachineOutliner.h.

Also, remove duplicate includes fr

LiveRegUnits.h - reduce MachineRegisterInfo.h include. NFC.

We only need to include MachineInstrBundle.h, but exposes an implicit dependency in MachineOutliner.h.

Also, remove duplicate includes from LiveRegUnits.cpp + MachineOutliner.cpp.

show more ...

[LiveRegUnits] Add phys_regs_and_masks iterator range (NFC).

This iterator range just includes physical registers and register masks,
which are interesting when dealing with register liveness.

Revi

[LiveRegUnits] Add phys_regs_and_masks iterator range (NFC).

This iterator range just includes physical registers and register masks,
which are interesting when dealing with register liveness.

Reviewers: evandro, t.p.northover, paquette, MatzeB, arsenm

Reviewed By: paquette

Differential Revision: https://reviews.llvm.org/D70562

show more ...

Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM

Summary:
This clang-tidy check is looking for unsigned integer variables whose initializer
starts with an implicit cast from llvm::Re

Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM

Summary:
This clang-tidy check is looking for unsigned integer variables whose initializer
starts with an implicit cast from llvm::Register and changes the type of the
variable to llvm::Register (dropping the llvm:: where possible).

Partial reverts in:
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
X86FixupLEAs.cpp - Some functions return unsigned and arguably should be MCRegister
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
HexagonBitSimplify.cpp - Function takes BitTracker::RegisterRef which appears to be unsigned&
MachineVerifier.cpp - Ambiguous operator==() given MCRegister and const Register
PPCFastISel.cpp - No Register::operator-=()
PeepholeOptimizer.cpp - TargetInstrInfo::optimizeLoadInstr() takes an unsigned&
MachineTraceMetrics.cpp - MachineTraceMetrics lacks a suitable constructor

Manual fixups in:
ARMFastISel.cpp - ARMEmitLoad() now takes a Register& instead of unsigned&
HexagonSplitDouble.cpp - Ternary operator was ambiguous between unsigned/Register
HexagonConstExtenders.cpp - Has a local class named Register, used llvm::Register instead of Register.
PPCFastISel.cpp - PPCEmitLoad() now takes a Register& instead of unsigned&

Depends on D65919

Reviewers: arsenm, bogner, craig.topper, RKSimon

Reviewed By: arsenm

Subscribers: RKSimon, craig.topper, lenary, aemerson, wuzish, jholewinski, MatzeB, qcolombet, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, wdng, nhaehnle, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, javed.absar, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, tpr, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, Jim, s.egerton, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D65962

llvm-svn: 369041

show more ...

Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC

llvm-svn: 367633

[CodeGen] Don't scavenge non-saved regs in exception throwing functions

Previously, LiveRegUnits was assuming that if a block has no successors
and does not return, then no registers are live at the

[CodeGen] Don't scavenge non-saved regs in exception throwing functions

Previously, LiveRegUnits was assuming that if a block has no successors
and does not return, then no registers are live at the end of it
(because the end of the block is unreachable). This was causing the
register scavenger to use callee-saved registers to materialise stack
frame addresses without saving them in the prologue. This would normally
be fine, because the end of the block is unreachable, but this is not
legal if the block ends by throwing a C++ exception. If this happens,
the scratch register will be modified, but its previous value won't be
preserved, so it doesn't get restored by the exception unwinder.

Differential revision: https://reviews.llvm.org/D57381

llvm-svn: 352844

show more ...

Update the file headers across all of the LLVM projects in the monorepo
to reflect the new license.

We understand that people may be surprised that we're moving the header
entirely to discuss the ne

Update the file headers across all of the LLVM projects in the monorepo
to reflect the new license.

We understand that people may be surprised that we're moving the header
entirely to discuss the new license. We checked this carefully with the
Foundation's lawyer and we believe this is the correct approach.

Essentially, all code in the project is now made available by the LLVM
project under our new license, so you will see that the license headers
include that license only. Some of our contributors have contributed
code under our old license, and accordingly, we have retained a copy of
our old license notice in the top-level files in each project and
repository.

llvm-svn: 351636

show more ...

[CodeGen] Avoid handling DBG_VALUE in LiveRegUnits::stepBackward

Patch by Jesper Antonsson.

Differential Revision: https://reviews.llvm.org/D48420

llvm-svn: 335233

Fix a bunch more layering of CodeGen headers that are in Target

All these headers already depend on CodeGen headers so moving them into
CodeGen fixes the layering (since CodeGen depends on Target, n

Fix a bunch more layering of CodeGen headers that are in Target

All these headers already depend on CodeGen headers so moving them into
CodeGen fixes the layering (since CodeGen depends on Target, not the
other way around).

llvm-svn: 318490

show more ...

Preserve existing regs when adding pristines to LivePhysRegs/LiveRegUnits

Differential Revision: https://reviews.llvm.org/D37600

llvm-svn: 312797

LiveRegUnits: Rename accumulateBackward()->accumulate()

Contrary to the stepForward()/stepBackward() method accumulate() doesn't
have a direction as defs, uses and clobbers all have the same effect.

LiveRegUnits: Rename accumulateBackward()->accumulate()

Contrary to the stepForward()/stepBackward() method accumulate() doesn't
have a direction as defs, uses and clobbers all have the same effect.

Also improve the documentation comment.

llvm-svn: 307351

show more ...

LiveRegUnits: Port recent LivePhysRegs bugfixes

Adjust code to look more like the code in LivePhysRegs and port over the
fix for LivePhysRegs from r304001 and adapt to the new CSR management in
Mach

LiveRegUnits: Port recent LivePhysRegs bugfixes

Adjust code to look more like the code in LivePhysRegs and port over the
fix for LivePhysRegs from r304001 and adapt to the new CSR management in
MachineRegisterInfo.

llvm-svn: 304622

show more ...

[CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).

llvm-svn: 295499

LiveRegUnits: Add accumulateBackward() function

Re-Commit r292543 with a fix for the situation when the chain end is
MBB.end().

This function can be used to accumulate the set of all read and modif

LiveRegUnits: Add accumulateBackward() function

Re-Commit r292543 with a fix for the situation when the chain end is
MBB.end().

This function can be used to accumulate the set of all read and modified
register in a sequence of instructions.

Use this code in AArch64A57FPLoadBalancing::scavengeRegister() to prove
the concept.

- The AArch64A57LoadBalancing code is using a backwards analysis now
which is irrespective of kill flags. This is the main motivation for
this change.

Differential Revision: http://reviews.llvm.org/D22082

llvm-svn: 292705

show more ...

Revert "LiveRegUnits: Add accumulateBackward() function"

This seems to be breaking some bots.

This reverts commit r292543.

llvm-svn: 292574

LiveRegUnits: Add accumulateBackward() function

This function can be used to accumulate the set of all read and modified
register in a sequence of instructions.

Use this code in AArch64A57FPLoadBal

LiveRegUnits: Add accumulateBackward() function

This function can be used to accumulate the set of all read and modified
register in a sequence of instructions.

Use this code in AArch64A57FPLoadBalancing::scavengeRegister() to prove
the concept.

- The AArch64A57LoadBalancing code is using a backwards analysis now
which is irrespective of kill flags. This is the main motivation for
this change.

Differential Revision: http://reviews.llvm.org/D22082

llvm-svn: 292543

show more ...

CodeGen: Add/Factor out LiveRegUnits class; NFCI

This is a set of register units intended to track register liveness, it
is similar in spirit to LivePhysRegs.
You can also think of this as the liven

CodeGen: Add/Factor out LiveRegUnits class; NFCI

This is a set of register units intended to track register liveness, it
is similar in spirit to LivePhysRegs.
You can also think of this as the liveness tracking parts of the
RegisterScavenger factored out into an own class.

This was proposed in http://llvm.org/PR27609

Differential Revision: http://reviews.llvm.org/D21916

llvm-svn: 292542

show more ...

CodeGen: Add/Factor out LiveRegUnits class; NFCI

This is a set of register units intended to track register liveness, it
is similar in spirit to LivePhysRegs.
You can also think of this as the liven

CodeGen: Add/Factor out LiveRegUnits class; NFCI

This is a set of register units intended to track register liveness, it
is similar in spirit to LivePhysRegs.
You can also think of this as the liveness tracking parts of the
RegisterScavenger factored out into an own class.

This was proposed in http://llvm.org/PR27609

Differential Revision: http://reviews.llvm.org/D21916

llvm-svn: 279171

show more ...

Revert "Convert liveness tracking to work on a sub-register level instead of just register units."

This reverts commit r197253.

This was a great change, but Juergen should be the commit author.

ll

Revert "Convert liveness tracking to work on a sub-register level instead of just register units."

This reverts commit r197253.

This was a great change, but Juergen should be the commit author.

llvm-svn: 197262

show more ...

LiveRegUnits: Use *MBB for consistency and convenience.

llvm-svn: 192634

LiveRegUnits::removeRegsInMask safety.

Clobbering is exclusive not inclusive on register units.
For liveness, we need to consider all the preserved registers.
e.g. A regmask that clobbers YMM0 may p

LiveRegUnits::removeRegsInMask safety.

Clobbering is exclusive not inclusive on register units.
For liveness, we need to consider all the preserved registers.
e.g. A regmask that clobbers YMM0 may preserve XMM0.
Units are only clobbered when all super-registers are clobbered.

llvm-svn: 192623

show more ...

Move LiveRegUnits implementation into .cpp. Comment and format.

llvm-svn: 192621