| /freebsd-src/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | DetectDeadLanes.h | 57 const VRegInfo &getVRegInfo(unsigned RegIdx) const { in getVRegInfo()
61 bool isDefinedByCopy(unsigned RegIdx) const { in isDefinedByCopy()
101 void PutInWorklist(unsigned RegIdx) { in PutInWorklist()
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| /freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | SplitKit.cpp | 509 ValueForcePair &VFP = Values[std::make_pair(RegIdx, ParentVNI.id)]; in forceRecompute() argument
472 defValue(unsigned RegIdx,const VNInfo * ParentVNI,SlotIndex Idx,bool Original) defValue() argument
549 buildCopy(Register FromReg,Register ToReg,LaneBitmask LaneMask,MachineBasicBlock & MBB,MachineBasicBlock::iterator InsertBefore,bool Late,unsigned RegIdx) buildCopy() argument
593 defFromParent(unsigned RegIdx,const VNInfo * ParentVNI,SlotIndex UseIdx,MachineBasicBlock & MBB,MachineBasicBlock::iterator I) defFromParent() argument
810 unsigned RegIdx = 0; leaveIntvAtTop() local
885 unsigned RegIdx = AssignI.value(); removeBackCopies() local
1147 unsigned RegIdx; transferValues() local
1286 unsigned RegIdx = RegAssign.lookup(V->def); extendPHIKillRanges() local
1301 unsigned RegIdx = RegAssign.lookup(V->def); extendPHIKillRanges() local
1324 unsigned RegIdx; rewriteAssigned() member
1348 unsigned RegIdx = RegAssign.lookup(Idx); rewriteAssigned() local
1514 unsigned RegIdx = RegAssign.lookup(ParentVNI->def); finish() local
[all...] |
| H A D | DetectDeadLanes.cpp | 279 unsigned RegIdx = Register::virtReg2Index(Reg); in determineInitialDefinedLanes() local
456 for (unsigned RegIdx = 0; RegIdx < NumVirtRegs; ++RegIdx) { in computeSubRegisterLaneBitInfo() local
467 unsigned RegIdx = Worklist.front(); in computeSubRegisterLaneBitInfo() local
509 unsigned RegIdx = Register::virtReg2Index(Reg); in modifySubRegisterOperandStatus() local
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| H A D | SplitKit.h | 349 LiveIntervalCalc &getLICalc(unsigned RegIdx) { in getLICalc()
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMCallingConv.cpp | 201 unsigned RegIdx = State.getFirstUnallocated(RegList); in CC_ARM_AAPCS_Custom_Aggregate() local
247 unsigned RegIdx = State.getFirstUnallocated(RegList); in CC_ARM_AAPCS_Custom_Aggregate() local
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| H A D | ARMISelLowering.cpp | 4525 unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs); LowerFormalArguments() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRAsmPrinter.cpp | 131 unsigned RegIdx = ByteNumber / BytesPerReg; PrintAsmOperand() local
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| H A D | AVRISelLowering.cpp | 1282 unsigned RegIdx = RegLastIdx + TotalBytes; analyzeArguments() local
1365 int RegIdx = TotalBytes - 1; analyzeReturnValues() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/ |
| H A D | AMDGPUDisassembler.cpp | 293 unsigned RegIdx = Imm & 0xff; DECODE_OPERAND_REG_8() local
304 unsigned RegIdx = Imm & 0x7f; DecodeVGPR_16_Lo128RegisterClass() local
318 unsigned RegIdx = Imm & 0x7f; decodeOperand_VSrcT16_Lo128() local
334 unsigned RegIdx = Imm & 0xff; decodeOperand_VSrcT16() local
1329 createVGPR16Operand(unsigned RegIdx,bool IsHi) const createVGPR16Operand() argument
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64CollectLOH.cpp | 547 int RegIdx = mapRegToGPRIndex(LI.PhysReg); in runOnMachineFunction() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelDAGToDAG.cpp | 841 SDValue RegIdx = Node->getOperand(2); trySelect() local
910 SDValue RegIdx = Node->getOperand(2); trySelect() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| H A D | AMDGPUMCCodeEmitter.cpp | 615 unsigned RegIdx = Encoding & AMDGPU::HWEncoding::REG_IDX_MASK; getMachineOpValueT16Lo128() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ExpandPseudo.cpp | 682 for (int64_t OpndIdx = 7, RegIdx = 0; ExpandVastartSaveXmmRegs() local
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| H A D | X86SpeculativeLoadHardening.cpp | 1864 unsigned RegIdx = Log2_32(RegBytes); canHardenRegister() local
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| H A D | X86FastISel.cpp | 2629 unsigned RegIdx = X86::sub_16bit; fastLowerIntrinsicCall() local
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| H A D | X86InstrInfo.cpp | 5768 unsigned RegIdx = UseMI.findRegisterUseOperandIdx(Reg); FoldImmediateImpl() local
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| H A D | X86ISelLowering.cpp | 35944 for (unsigned RegIdx = 0; SavedRegs[RegIdx]; ++RegIdx) { EmitSjLjDispatchBlock() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/LiveDebugValues/ |
| H A D | VarLocBasedImpl.cpp | 1456 LocIndex RegIdx = LocIndex::fromRawInteger(*It); in collectAllVarLocs() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 3592 unsigned RegIdx = State.getFirstUnallocated(ArgGPRs); CC_LoongArch() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 2685 unsigned RegIdx = RegNum / AlignSize; getRegularReg() local
4718 auto RegIdx = Reg - (VGPR32.contains(Reg) ? AMDGPU::VGPR0 : AMDGPU::AGPR0); validateGWS() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 891 struct RegIdxOp RegIdx; member
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 2235 unsigned RegIdx = CCInfo.getFirstUnallocated(ArgVGPRs); allocateVGPR32Input() local
2257 unsigned RegIdx = CCInfo.getFirstUnallocated(ArgSGPRs); allocateSGPR32InputImpl() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 6748 unsigned RegIdx = 3; shouldOmitPredicateOperand() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 17509 unsigned RegIdx = State.getFirstUnallocated(ArgGPRs); CC_RISCV() local
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