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Searched defs:Reg0 (Results 1 – 25 of 27) sorted by relevance

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/llvm-project/llvm/unittests/tools/llvm-exegesis/Mips/
H A DTargetTest.cpp87 const unsigned Reg0 = Mips::T0; in TEST_F() local
99 const unsigned Reg0 = Mips::T0_64; in TEST_F() local
/llvm-project/llvm/lib/Target/X86/
H A DX86FixupSetCC.cpp89 Register Reg0 = MI.getOperand(0).getReg(); in runOnMachineFunction() local
H A DX86CompressEVEX.cpp193 Register Reg0 = MI.getOperand(0).getReg(); CompressEVEXImpl() local
H A DX86ExpandPseudo.cpp467 Register Reg0 = TRI->getSubReg(Reg, X86::sub_mask_0); expandMI() local
503 Register Reg0 = TRI->getSubReg(Reg, X86::sub_mask_0); expandMI() local
/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp175 emitR(unsigned Opcode,unsigned Reg0,SMLoc IDLoc,const MCSubtargetInfo * STI) emitR() argument
184 emitRX(unsigned Opcode,unsigned Reg0,MCOperand Op1,SMLoc IDLoc,const MCSubtargetInfo * STI) emitRX() argument
194 emitRI(unsigned Opcode,unsigned Reg0,int32_t Imm,SMLoc IDLoc,const MCSubtargetInfo * STI) emitRI() argument
199 emitRR(unsigned Opcode,unsigned Reg0,unsigned Reg1,SMLoc IDLoc,const MCSubtargetInfo * STI) emitRR() argument
214 emitRRX(unsigned Opcode,unsigned Reg0,unsigned Reg1,MCOperand Op2,SMLoc IDLoc,const MCSubtargetInfo * STI) emitRRX() argument
226 emitRRR(unsigned Opcode,unsigned Reg0,unsigned Reg1,unsigned Reg2,SMLoc IDLoc,const MCSubtargetInfo * STI) emitRRR() argument
232 emitRRRX(unsigned Opcode,unsigned Reg0,unsigned Reg1,unsigned Reg2,MCOperand Op3,SMLoc IDLoc,const MCSubtargetInfo * STI) emitRRRX() argument
245 emitRRI(unsigned Opcode,unsigned Reg0,unsigned Reg1,int16_t Imm,SMLoc IDLoc,const MCSubtargetInfo * STI) emitRRI() argument
251 emitRRIII(unsigned Opcode,unsigned Reg0,unsigned Reg1,int16_t Imm0,int16_t Imm1,int16_t Imm2,SMLoc IDLoc,const MCSubtargetInfo * STI) emitRRIII() argument
[all...]
H A DMipsMCCodeEmitter.cpp97 unsigned Reg0 = Ctx.getRegisterInfo()->getEncodingValue(RegOp0); in LowerCompactBranch() local
/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp233 Register Reg0 = Op0.getReg(); runOnMachineFunction() local
H A DHexagonBitTracker.cpp314 unsigned Reg0 = Reg[0].Reg; evaluate() local
/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVLegalizerInfo.cpp345 Register Reg0 = Op0.getReg(); legalizeCustom() local
/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp2173 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); SelectVLD() local
2308 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); SelectVST() local
2480 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); SelectVLDSTLane() local
3018 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); SelectVLDDup() local
3367 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); tryV6T2BitfieldExtractOp() local
3415 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); tryV6T2BitfieldExtractOp() local
3437 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); tryV6T2BitfieldExtractOp() local
3458 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); tryV6T2BitfieldExtractOp() local
3808 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); Select() local
3827 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); Select() local
5192 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); Select() local
5203 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); Select() local
5782 Register Reg0 = cast<RegisterSDNode>(V0)->getReg(); tryInlineAsm() local
[all...]
H A DThumb2SizeReduction.cpp754 Register Reg0 = MI->getOperand(0).getReg(); ReduceTo2Addr() local
H A DARMAsmPrinter.cpp336 Register Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0); PrintAsmOperand() local
/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp234 Register Reg0 = cast<RegisterSDNode>(V0)->getReg(); tryInlineAsm() local
/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEFrameLowering.cpp462 unsigned Reg0 = emitPrologue() local
480 unsigned Reg0 = MRI->getDwarfRegNum(Reg, true); emitPrologue() local
/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp200 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg(); in selectInlineAsm() local
/llvm-project/llvm/unittests/CodeGen/GlobalISel/
H A DPatternMatchTest.cpp297 Register Reg0; TEST_F() local
322 Register Reg0; TEST_F() local
/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp1218 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); InsertSEH() local
1231 Register Reg0 = MBBI->getOperand(1).getReg(); InsertSEH() local
1269 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg()); InsertSEH() local
1280 Register Reg0 = MBBI->getOperand(0).getReg(); InsertSEH() local
1314 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg()); InsertSEH() local
1327 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); InsertSEH() local
[all...]
/llvm-project/llvm/lib/CodeGen/
H A DMachineInstr.cpp2522 Register Reg0 = getOperand(0).getReg(); getFirst2RegLLTs() local
2530 Register Reg0 = getOperand(0).getReg(); getFirst3RegLLTs() local
2540 Register Reg0 = getOperand(0).getReg(); getFirst4RegLLTs() local
2552 Register Reg0 = getOperand(0).getReg(); getFirst5RegLLTs() local
[all...]
H A DRegAllocFast.cpp1339 Register Reg0 = MO0.getReg(); findAndSortDefOperandIndexes() local
H A DTargetInstrInfo.cpp185 Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register(); in commuteInstructionImpl() local
/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.cpp1494 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); printVectorListTwo() local
1507 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); printVectorListTwoSpaced() local
1562 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); printVectorListTwoAllLanes() local
1609 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); printVectorListTwoSpacedAllLanes() local
/llvm-project/llvm/include/llvm/MC/
H A DMCRegisterInfo.h701 uint16_t Reg0 = 0; global() variable
/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFoldOperands.cpp985 Register Reg0 = UseMI->getOperand(0).getReg(); foldOperand() local
/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp2229 Register Reg0 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass); loadImmediate() local
/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp1158 Register Reg0 = MI.getOperand(0).getReg(); commuteInstructionImpl() local
1188 Register Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg(); commuteInstructionImpl() local

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