Lines Matching defs:Reg0

2164   SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2183       // VLD1/VLD2 fixed increment does not need Reg0 so only include it in
2186         Ops.push_back(Reg0);
2189     Ops.push_back(Reg0);
2202     const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
2215       Ops.push_back(Reg0);
2219     Ops.push_back(Reg0);
2299   SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2343       // VST1/VST2 fixed increment does not need Reg0 so only include it in
2346         Ops.push_back(Reg0);
2350     Ops.push_back(Reg0);
2375   const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain };
2390     Ops.push_back(Reg0);
2394   Ops.push_back(Reg0);
2471   SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2480     Ops.push_back(IsImmUpdate ? Reg0 : Inc);
2504   Ops.push_back(Reg0);
3009   SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
3023         Ops.push_back(Reg0);
3035     const SDValue OpsA[] = {MemAddr, Align, ImplDef, Pred, Reg0, Chain};
3043   Ops.push_back(Reg0);
3358         SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
3366                               getAL(CurDAG, dl), Reg0, Reg0 };
3377                             getAL(CurDAG, dl), Reg0, Reg0 };
3386                           getAL(CurDAG, dl), Reg0 };
3406       SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
3411                         getAL(CurDAG, dl), Reg0 };
3428       SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
3433                         getAL(CurDAG, dl), Reg0 };
3449     SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
3454                       getAL(CurDAG, dl), Reg0 };
3803         SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
3805           SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG, dl), Reg0, Reg0 };
3809           SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG, dl), Reg0,
3810                             Reg0 };
3822         SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
3824           SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG, dl), Reg0, Reg0 };
3828           SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG, dl), Reg0,
3829                             Reg0 };
5176       SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
5177       SDValue Ops[] = { Src, Src, Pred, Reg0 };
5187       SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
5188       SDValue Ops[] = { Src, Pred, Reg0 };
5766     Register Reg0 = cast<RegisterSDNode>(V0)->getReg();
5788       SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0,
5802       SDValue T0 = CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32,