| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64PBQPRegAlloc.cpp | 158 addIntraChainConstraint(PBQPRAGraph & G,unsigned Rd,unsigned Ra) addIntraChainConstraint() argument
242 addInterChainConstraint(PBQPRAGraph & G,unsigned Rd,unsigned Ra) addInterChainConstraint() argument
362 Register Rd = MI.getOperand(0).getReg(); apply() local
372 Register Rd = MI.getOperand(0).getReg(); apply() local
[all...] |
| /freebsd-src/contrib/llvm-project/compiler-rt/lib/xray/ |
| H A D | xray_loongarch64.cpp | 31 encodeInstruction2RIx(uint32_t Opcode, uint32_t Rd, uint32_t Rj, in encodeInstruction2RIx()
38 encodeInstruction1RI20(uint32_t Opcode, uint32_t Rd, in encodeInstruction1RI20()
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| H A D | xray_mips.cpp | 47 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction()
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| H A D | xray_mips64.cpp | 48 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction()
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| /freebsd-src/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/ |
| H A D | RISCVInstructions.h | 22 struct Rd { struct
45 Rd rd; \ argument
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| H A D | RISCVCInstructions.h | 25 operator Rd() { return Rd{rd + (shift ? 8 : 0)}; } in Rd() function
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64Disassembler.cpp | 954 unsigned Rd = fieldFromInstruction(Insn, 0, 5); DecodeFMOVLaneInstruction() local
1053 unsigned Rd = fieldFromInstruction(insn, 0, 5); DecodeThreeAddrSRegInstruction() local
1115 unsigned Rd = fieldFromInstruction(insn, 0, 5); DecodeMoveImmInstruction() local
1655 unsigned Rd = fieldFromInstruction(insn, 0, 5); DecodeAddSubERegInstruction() local
1712 unsigned Rd = fieldFromInstruction(insn, 0, 5); DecodeLogicalImmInstruction() local
1743 unsigned Rd = fieldFromInstruction(insn, 0, 5); DecodeModImmInstruction() local
1782 unsigned Rd = fieldFromInstruction(insn, 0, 5); DecodeModImmTiedInstruction() local
1800 unsigned Rd = fieldFromInstruction(insn, 0, 5); DecodeAdrInstruction() local
1818 unsigned Rd = fieldFromInstruction(insn, 0, 5); DecodeAddSubImmShift() local
2049 unsigned Rd = fieldFromInstruction(insn, 0, 5); DecodeCPYMemOpInstruction() local
2074 unsigned Rd = fieldFromInstruction(insn, 0, 5); DecodeSETMemOpInstruction() local
[all...] |
| /freebsd-src/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/ |
| H A D | EmulateInstructionARM.cpp | 1168 uint32_t Rd; // the destination register in EmulateADDRdSPImm() local
1229 uint32_t Rd; // the destination register in EmulateMOVRdSP() local
1289 uint32_t Rd; // the destination register EmulateMOVRdRm() local
1377 uint32_t Rd; // the destination register EmulateMOVRdImm() local
1619 uint32_t Rd; // the destination register EmulateMVNImm() local
1681 uint32_t Rd; // the destination register EmulateMVNReg() local
2397 uint32_t Rd; EmulateSUBSPImm() local
3152 uint32_t Rd, Rn; EmulateADDImmARM() local
3218 uint32_t Rd, Rn, Rm; EmulateADDReg() local
3753 uint32_t Rd; // the destination register EmulateShiftImm() local
3838 uint32_t Rd; // the destination register EmulateShiftReg() local
5801 uint32_t Rd, Rn; EmulateADCImm() local
5871 uint32_t Rd, Rn, Rm; EmulateADCReg() local
5950 uint32_t Rd; EmulateADR() local
6018 uint32_t Rd, Rn; EmulateANDImm() local
6094 uint32_t Rd, Rn, Rm; EmulateANDReg() local
6183 uint32_t Rd, Rn; EmulateBICImm() local
6259 uint32_t Rd, Rn, Rm; EmulateBICReg() local
8822 uint32_t Rd, Rn; EmulateEORImm() local
8901 uint32_t Rd, Rn, Rm; EmulateEORReg() local
8991 uint32_t Rd, Rn; EmulateORRImm() local
9068 uint32_t Rd, Rn, Rm; EmulateORRReg() local
9155 uint32_t Rd; // the destination register EmulateRSBImm() local
9228 uint32_t Rd; // the destination register EmulateRSBReg() local
9306 uint32_t Rd; // the destination register EmulateRSCImm() local
9366 uint32_t Rd; // the destination register EmulateRSCReg() local
9435 uint32_t Rd; // the destination register EmulateSBCImm() local
9504 uint32_t Rd; // the destination register EmulateSBCReg() local
9584 uint32_t Rd; // the destination register EmulateSUBImmThumb() local
9678 uint32_t Rd; // the destination register EmulateSUBImmARM() local
14216 WriteCoreRegOptionalFlags(Context & context,const uint32_t result,const uint32_t Rd,bool setflags,const uint32_t carry,const uint32_t overflow) WriteCoreRegOptionalFlags() argument
[all...] |
| H A D | EmulateInstructionARM.h | 202 const uint32_t Rd) { in WriteCoreReg()
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 2429 unsigned Rd = fieldFromInstruction(Insn, 12, 4); DecodeQADDInstruction() local
2685 unsigned Rd = fieldFromInstruction(Insn, 8, 4); DecodeT2MOVTWInstruction() local
2710 unsigned Rd = fieldFromInstruction(Insn, 12, 4); DecodeArmMOVTWInstruction() local
2738 unsigned Rd = fieldFromInstruction(Insn, 16, 4); DecodeSMLAInstruction() local
2962 unsigned Rd = fieldFromInstruction(Insn, 12, 4); DecodeVLDInstruction() local
3294 unsigned Rd = fieldFromInstruction(Insn, 12, 4); DecodeVSTInstruction() local
3565 unsigned Rd = fieldFromInstruction(Insn, 12, 4); DecodeVLD1DupInstruction() local
3613 unsigned Rd = fieldFromInstruction(Insn, 12, 4); DecodeVLD2DupInstruction() local
3662 unsigned Rd = fieldFromInstruction(Insn, 12, 4); DecodeVLD3DupInstruction() local
3698 unsigned Rd = fieldFromInstruction(Insn, 12, 4); DecodeVLD4DupInstruction() local
3751 unsigned Rd = fieldFromInstruction(Insn, 12, 4); DecodeVMOVModImmInstruction() local
3852 unsigned Rd = fieldFromInstruction(Insn, 12, 4); DecodeVSHLMaxInstruction() local
3900 unsigned Rd = fieldFromInstruction(Insn, 12, 4); DecodeTBLInstruction() local
5117 unsigned Rd = fieldFromInstruction(Insn, 12, 4); DecodeDoubleRegStore() local
5250 unsigned Rd = fieldFromInstruction(Insn, 12, 4); DecodeVLD1LN() local
5317 unsigned Rd = fieldFromInstruction(Insn, 12, 4); DecodeVST1LN() local
5382 unsigned Rd = fieldFromInstruction(Insn, 12, 4); DecodeVLD2LN() local
5449 unsigned Rd = fieldFromInstruction(Insn, 12, 4); DecodeVST2LN() local
5512 unsigned Rd = fieldFromInstruction(Insn, 12, 4); DecodeVLD3LN() local
5582 unsigned Rd = fieldFromInstruction(Insn, 12, 4); DecodeVST3LN() local
5645 unsigned Rd = fieldFromInstruction(Insn, 12, 4); DecodeVLD4LN() local
5726 unsigned Rd = fieldFromInstruction(Insn, 12, 4); DecodeVST4LN() local
5950 const unsigned Rd = fieldFromInstruction(Insn, 8, 4); DecodeT2Adr() local
7002 const unsigned Rd = fieldFromInstruction(Insn, 8, 4); DecodeT2AddSubSPImm() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/Disassembler/ |
| H A D | RISCVDisassembler.cpp | 382 uint32_t Rd = fieldFromInstruction(Insn, 7, 5); decodeRVCInstrRdRs1ImmZero() local
429 uint32_t Rd = fieldFromInstruction(Insn, 7, 5); decodeRVCInstrRdRs2() local
439 uint32_t Rd = fieldFromInstruction(Insn, 7, 5); decodeRVCInstrRdRs1Rs2() local
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| /freebsd-src/sys/arm64/arm64/ |
| H A D | undefined.c | 206 int attempts, error, Rn, Rd, Rm; in swp_emulate() local
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/MSP430/Disassembler/ |
| H A D | MSP430Disassembler.cpp | 194 unsigned Rd = fieldFromInstruction(Insn, 0, 4); in DecodeDstAddrMode() local
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/ |
| H A D | HexagonAsmParser.cpp | 1689 MCOperand &Rd = Inst.getOperand(0); processInstruction() local
1722 MCOperand &Rd = Inst.getOperand(0); processInstruction() local
1732 MCOperand &Rd = Inst.getOperand(0); processInstruction() local
1920 MCOperand &Rd = Inst.getOperand(0); processInstruction() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/LoongArch/AsmParser/ |
| H A D | LoongArchAsmParser.cpp | 1226 unsigned Rd = Inst.getOperand(0).getReg(); checkTargetMatchPredicate() local
1238 unsigned Rd = Inst.getOperand(0).getReg(); checkTargetMatchPredicate() local
|
| /freebsd-src/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM64/ |
| H A D | EmulateInstructionARM64.cpp | 620 const uint32_t Rd = Bits32(opcode, 4, 0); EmulateADDSUBImm() local
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonConstExtenders.cpp | 325 Register Rd; member
[all...] |
| H A D | HexagonFrameLowering.cpp | 2511 Register Rd = RdOp.getReg(), Rs = RsOp.getReg(); expandAlloca() local
[all...] |
| H A D | HexagonInstrInfo.cpp | 1344 Register Rd = Op0.getReg(); expandPostRAPseudo() local
[all...] |