Lines Matching defs:Rd
501 unsigned Rd = fieldFromInstruction(Insn, 0, 5);
507 Inst, Rd, Address, Decoder);
512 Inst, Rd, Address, Decoder);
604 unsigned Rd = fieldFromInstruction(insn, 0, 5);
632 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rd, Addr,
656 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr,
672 unsigned Rd = fieldFromInstruction(insn, 0, 5);
684 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rd, Addr,
690 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr,
1256 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1270 DecodeSimpleRegisterClass<AArch64::GPR32spRegClassID, 0, 32>(Inst, Rd, Addr,
1279 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rd, Addr,
1288 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rd, Addr,
1297 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr,
1306 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rd, Addr,
1315 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr,
1331 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1338 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr,
1342 Inst, Rd, Addr, Decoder);
1350 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rd, Addr,
1354 Inst, Rd, Addr, Decoder);
1368 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1374 DecodeSimpleRegisterClass<AArch64::FPR64RegClassID, 0, 32>(Inst, Rd, Addr,
1377 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rd, Addr,
1409 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1415 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rd, Addr,
1417 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rd, Addr,
1429 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1437 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr,
1448 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1461 if (Rd == 31 && !S)
1463 Inst, Rd, Addr, Decoder);
1465 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr,
1470 if (Rd == 31 && !S)
1472 Inst, Rd, Addr, Decoder);
1474 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rd, Addr,
1688 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1694 if (Rd == Rs || Rs == Rn || Rd == Rn)
1700 Inst, Rd, Addr, Decoder) ||
1706 Inst, Rd, Addr, Decoder) ||
1719 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1725 if (Rd == Rm || Rm == Rn || Rd == Rn)
1728 // Rd and Rn (not Rm) register operands are written back, so they appear
1731 Inst, Rd, Addr, Decoder) ||
1735 Inst, Rd, Addr, Decoder) ||