Lines Matching defs:Rd
1168 uint32_t Rd; // the destination register
1172 Rd = 7;
1176 Rd = Bits32(opcode, 15, 12);
1186 if (Rd == GetFramePointerRegisterNumber())
1194 if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + Rd,
1229 uint32_t Rd; // the destination register
1232 Rd = 7;
1235 Rd = 12;
1242 if (Rd == GetFramePointerRegisterNumber())
1250 if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + Rd, sp))
1289 uint32_t Rd; // the destination register
1293 Rd = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0);
1296 if (Rd == 15 && InITBlock() && !LastInITBlock())
1300 Rd = Bits32(opcode, 2, 0);
1307 Rd = Bits32(opcode, 11, 8);
1311 if (setflags && (BadReg(Rd) || BadReg(Rm)))
1315 if (!setflags && (Rd == 15 || Rm == 15 || (Rd == 13 && Rm == 13)))
1319 Rd = Bits32(opcode, 15, 12);
1323 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related
1325 if (Rd == 15 && setflags)
1335 // The context specifies that Rm is to be moved into Rd.
1337 if (Rd == 13)
1339 else if (Rd == GetFramePointerRegisterNumber() && Rm == 13)
1347 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags))
1377 uint32_t Rd; // the destination register
1378 uint32_t imm32; // the immediate value to be written to Rd
1386 Rd = Bits32(opcode, 10, 8);
1394 Rd = Bits32(opcode, 11, 8);
1397 if (BadReg(Rd))
1403 // d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(imm4:i:imm3:imm8,
1405 Rd = Bits32(opcode, 11, 8);
1414 if (BadReg(Rd))
1419 // d = UInt(Rd); setflags = (S == '1'); (imm32, carry) =
1421 Rd = Bits32(opcode, 15, 12);
1425 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related
1427 if ((Rd == 15) && setflags)
1433 // d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(imm4:imm12, 32);
1434 Rd = Bits32(opcode, 15, 12);
1441 if (Rd == 15)
1450 // The context specifies that an immediate is to be moved into Rd.
1455 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
1509 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = FALSE;
1522 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S == '1');
1619 uint32_t Rd; // the destination register
1625 Rd = Bits32(opcode, 11, 8);
1630 Rd = Bits32(opcode, 15, 12);
1634 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related
1636 if (Rd == 15 && setflags)
1644 // The context specifies that an immediate is to be moved into Rd.
1649 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
1681 uint32_t Rd; // the destination register
1688 Rd = Bits32(opcode, 2, 0);
1697 Rd = Bits32(opcode, 11, 8);
1702 if (BadReg(Rd) || BadReg(Rm))
1706 Rd = Bits32(opcode, 15, 12);
1725 // The context specifies that an immediate is to be moved into Rd.
1730 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
1858 // d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(imm8:'00', 32);
1872 // d = UInt(Rd); setflags = (S == "1"); imm32 =
1878 // if Rd == "1111" && S == "1" then SEE CMN (immediate);
1889 // d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(i:imm3:imm8, 32);
2369 // If Rd == 13 => A sub operation to adjust the SP -- allocate space for local
2397 uint32_t Rd;
2402 Rd = 13;
2407 Rd = Bits32(opcode, 11, 8);
2410 if (Rd == 15 && setflags)
2412 if (Rd == 15 && !setflags)
2416 Rd = Bits32(opcode, 11, 8);
2419 if (Rd == 15)
2423 Rd = Bits32(opcode, 15, 12);
2427 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related
2429 if (Rd == 15 && setflags)
2438 if (Rd == 13) {
2449 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags,
3036 // d = UInt(Rd); n = UInt(Rn); setflags = !InITBlock(); imm32 =
3056 // if Rd == '1111' && S == '1' then SEE CMN (immediate);
3057 // d = UInt(Rd); n = UInt(Rn); setflags = (S == '1'); imm32 =
3076 // d = UInt(Rd); n = UInt(Rn); setflags = FALSE; imm32 =
3152 uint32_t Rd, Rn;
3158 Rd = Bits32(opcode, 15, 12);
3175 if (Rd == 13)
3177 else if (Rd == GetFramePointerRegisterNumber())
3186 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags,
3218 uint32_t Rd, Rn, Rm;
3224 Rd = Bits32(opcode, 2, 0);
3232 Rd = Rn = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0);
3239 if (Rd == 15 && InITBlock() && !LastInITBlock())
3243 Rd = Bits32(opcode, 15, 12);
3276 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags,
3753 uint32_t Rd; // the destination register
3771 Rd = Bits32(opcode, 2, 0);
3782 Rd = Bits32(opcode, 11, 8);
3786 if (BadReg(Rd) || BadReg(Rm))
3790 Rd = Bits32(opcode, 15, 12);
3816 // The context specifies that an immediate is to be moved into Rd.
3821 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
3838 uint32_t Rd; // the destination register
3846 Rd = Bits32(opcode, 2, 0);
3847 Rn = Rd;
3852 Rd = Bits32(opcode, 11, 8);
3856 if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
3860 Rd = Bits32(opcode, 15, 12);
3864 if (Rd == 15 || Rn == 15 || Rm == 15)
3887 // The context specifies that an immediate is to be moved into Rd.
3892 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
5801 uint32_t Rd, Rn;
5807 Rd = Bits32(opcode, 11, 8);
5811 if (BadReg(Rd) || BadReg(Rn))
5815 Rd = Bits32(opcode, 15, 12);
5820 if (Rd == 15 && setflags)
5838 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags,
5871 uint32_t Rd, Rn, Rm;
5877 Rd = Rn = Bits32(opcode, 2, 0);
5884 Rd = Bits32(opcode, 11, 8);
5889 if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
5893 Rd = Bits32(opcode, 15, 12);
5899 if (Rd == 15 && setflags)
5925 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags,
5950 uint32_t Rd;
5955 Rd = Bits32(opcode, 10, 8);
5961 Rd = Bits32(opcode, 11, 8);
5964 if (BadReg(Rd))
5969 Rd = Bits32(opcode, 15, 12);
5988 if (!WriteCoreReg(context, result, Rd))
6018 uint32_t Rd, Rn;
6025 Rd = Bits32(opcode, 11, 8);
6031 // if Rd == '1111' && S == '1' then SEE TST (immediate);
6032 if (Rd == 15 && setflags)
6034 if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn))
6038 Rd = Bits32(opcode, 15, 12);
6045 if (Rd == 15 && setflags)
6063 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
6094 uint32_t Rd, Rn, Rm;
6101 Rd = Rn = Bits32(opcode, 2, 0);
6108 Rd = Bits32(opcode, 11, 8);
6113 // if Rd == '1111' && S == '1' then SEE TST (register);
6114 if (Rd == 15 && setflags)
6116 if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn) || BadReg(Rm))
6120 Rd = Bits32(opcode, 15, 12);
6126 if (Rd == 15 && setflags)
6152 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
6183 uint32_t Rd, Rn;
6190 Rd = Bits32(opcode, 11, 8);
6196 if (BadReg(Rd) || BadReg(Rn))
6200 Rd = Bits32(opcode, 15, 12);
6207 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related
6209 if (Rd == 15 && setflags)
6227 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
6259 uint32_t Rd, Rn, Rm;
6266 Rd = Rn = Bits32(opcode, 2, 0);
6273 Rd = Bits32(opcode, 11, 8);
6278 if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
6282 Rd = Bits32(opcode, 15, 12);
6288 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related
6290 if (Rd == 15 && setflags)
6316 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
8340 // d = UInt(Rd); m = UInt(Rm); rotation = 0;
8348 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
8360 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
8425 // d = UInt(Rd); m = UInt(Rm); rotation = 0;
8433 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
8445 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
8510 // d = UInt(Rd); m = UInt(Rm); rotation = 0;
8518 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
8530 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
8592 // d = UInt(Rd); m = UInt(Rm); rotation = 0;
8600 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
8612 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
8822 uint32_t Rd, Rn;
8829 Rd = Bits32(opcode, 11, 8);
8835 // if Rd == '1111' && S == '1' then SEE TEQ (immediate);
8836 if (Rd == 15 && setflags)
8838 if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn))
8842 Rd = Bits32(opcode, 15, 12);
8849 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related
8851 if (Rd == 15 && setflags)
8869 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
8901 uint32_t Rd, Rn, Rm;
8908 Rd = Rn = Bits32(opcode, 2, 0);
8915 Rd = Bits32(opcode, 11, 8);
8920 // if Rd == '1111' && S == '1' then SEE TEQ (register);
8921 if (Rd == 15 && setflags)
8923 if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn) || BadReg(Rm))
8927 Rd = Bits32(opcode, 15, 12);
8933 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related
8935 if (Rd == 15 && setflags)
8961 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
8991 uint32_t Rd, Rn;
8998 Rd = Bits32(opcode, 11, 8);
9007 if (BadReg(Rd) || Rn == 13)
9011 Rd = Bits32(opcode, 15, 12);
9018 if (Rd == 15 && setflags)
9036 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
9068 uint32_t Rd, Rn, Rm;
9075 Rd = Rn = Bits32(opcode, 2, 0);
9082 Rd = Bits32(opcode, 11, 8);
9090 if (BadReg(Rd) || Rn == 13 || BadReg(Rm))
9094 Rd = Bits32(opcode, 15, 12);
9100 if (Rd == 15 && setflags)
9126 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
9155 uint32_t Rd; // the destination register
9162 Rd = Bits32(opcode, 2, 0);
9168 Rd = Bits32(opcode, 11, 8);
9172 if (BadReg(Rd) || BadReg(Rn))
9176 Rd = Bits32(opcode, 15, 12);
9181 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related
9183 if (Rd == 15 && setflags)
9200 return WriteCoreRegOptionalFlags(context, res.result, Rd, setflags,
9228 uint32_t Rd; // the destination register
9236 Rd = Bits32(opcode, 11, 8);
9242 if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
9246 Rd = Bits32(opcode, 15, 12);
9252 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related
9254 if (Rd == 15 && setflags)
9278 return WriteCoreRegOptionalFlags(context, res.result, Rd, setflags,
9306 uint32_t Rd; // the destination register
9313 Rd = Bits32(opcode, 15, 12);
9318 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related
9320 if (Rd == 15 && setflags)
9337 return WriteCoreRegOptionalFlags(context, res.result, Rd, setflags,
9366 uint32_t Rd; // the destination register
9374 Rd = Bits32(opcode, 15, 12);
9380 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related
9382 if (Rd == 15 && setflags)
9406 return WriteCoreRegOptionalFlags(context, res.result, Rd, setflags,
9435 uint32_t Rd; // the destination register
9442 Rd = Bits32(opcode, 11, 8);
9446 if (BadReg(Rd) || BadReg(Rn))
9450 Rd = Bits32(opcode, 15, 12);
9455 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related
9457 if (Rd == 15 && setflags)
9474 return WriteCoreRegOptionalFlags(context, res.result, Rd, setflags,
9504 uint32_t Rd; // the destination register
9512 Rd = Rn = Bits32(opcode, 2, 0);
9519 Rd = Bits32(opcode, 11, 8);
9524 if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
9528 Rd = Bits32(opcode, 15, 12);
9534 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related
9536 if (Rd == 15 && setflags)
9560 return WriteCoreRegOptionalFlags(context, res.result, Rd, setflags,
9584 uint32_t Rd; // the destination register
9591 Rd = Bits32(opcode, 2, 0);
9597 Rd = Rn = Bits32(opcode, 10, 8);
9602 Rd = Bits32(opcode, 11, 8);
9607 // if Rd == '1111' && S == '1' then SEE CMP (immediate);
9608 if (Rd == 15 && setflags)
9616 if (Rd == 13 || (Rd == 15 && !setflags) || Rn == 15)
9620 Rd = Bits32(opcode, 11, 8);
9633 if (BadReg(Rd))
9650 return WriteCoreRegOptionalFlags(context, res.result, Rd, setflags,
9678 uint32_t Rd; // the destination register
9685 Rd = Bits32(opcode, 15, 12);
9698 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related
9700 if (Rd == 15 && setflags)
9714 if (Rd == 13)
9724 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags,
10017 // d = UInt(Rd); m = UInt(Rm); setflags = (S == '1');
10036 // d = UInt(Rd); m = UInt(Rm); setflags = (S == '1');
10041 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related
10114 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); s = UInt(Rs);
10212 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = !InITBlock();
10225 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S =="1");
10231 // if Rd == "1111" && S == "1" then SEE CMP (register);
10252 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S == '1');
10258 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related
10340 // d = UInt(Rd); t = UInt(Rt); n = UInt(Rn); imm32 =
10359 // d = UInt(Rd); t = UInt(Rt); n = UInt(Rn); imm32 = Zeros(32); // Zero
12839 "sub{s}<c> <Rd>, sp, <Rm>{,<shift>}"},
12888 &EmulateInstructionARM::EmulateADCImm, "adc{s}<c> <Rd>, <Rn>, #const"},
12892 "adc{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12896 "add{s}<c> <Rd>, <Rn>, #const"},
12900 "add{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12904 "add{s}<c> <Rd>, <Rn>, <Rm>, <type> <RS>"},
12907 &EmulateInstructionARM::EmulateADR, "add<c> <Rd>, PC, #<const>"},
12909 &EmulateInstructionARM::EmulateADR, "sub<c> <Rd>, PC, #<const>"},
12912 &EmulateInstructionARM::EmulateANDImm, "and{s}<c> <Rd>, <Rn>, #const"},
12916 "and{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12919 &EmulateInstructionARM::EmulateBICImm, "bic{s}<c> <Rd>, <Rn>, #const"},
12923 "bic{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12926 &EmulateInstructionARM::EmulateEORImm, "eor{s}<c> <Rd>, <Rn>, #const"},
12930 "eor{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12933 &EmulateInstructionARM::EmulateORRImm, "orr{s}<c> <Rd>, <Rn>, #const"},
12937 "orr{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12940 &EmulateInstructionARM::EmulateRSBImm, "rsb{s}<c> <Rd>, <Rn>, #<const>"},
12944 "rsb{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12947 &EmulateInstructionARM::EmulateRSCImm, "rsc{s}<c> <Rd>, <Rn>, #<const>"},
12951 "rsc{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12954 &EmulateInstructionARM::EmulateSBCImm, "sbc{s}<c> <Rd>, <Rn>, #<const>"},
12958 "sbc{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12962 "sub{s}<c> <Rd>, <Rn>, #<const>"},
12965 &EmulateInstructionARM::EmulateSUBSPImm, "sub{s}<c> <Rd>, sp, #<const>"},
12969 "sub{s}<c> <Rd>, <Rn>, <Rm>{,<shift>}"},
12985 &EmulateInstructionARM::EmulateMOVRdImm, "mov{s}<c> <Rd>, #<const>"},
12987 &EmulateInstructionARM::EmulateMOVRdImm, "movw<c> <Rd>, #<imm16>"},
12990 &EmulateInstructionARM::EmulateMOVRdRm, "mov{s}<c> <Rd>, <Rm>"},
12993 &EmulateInstructionARM::EmulateMVNImm, "mvn{s}<c> <Rd>, #<const>"},
12997 "mvn{s}<c> <Rd>, <Rm> {,<shift>}"},
13012 &EmulateInstructionARM::EmulateASRImm, "asr{s}<c> <Rd>, <Rm>, #imm"},
13015 &EmulateInstructionARM::EmulateASRReg, "asr{s}<c> <Rd>, <Rn>, <Rm>"},
13018 &EmulateInstructionARM::EmulateLSLImm, "lsl{s}<c> <Rd>, <Rm>, #imm"},
13021 &EmulateInstructionARM::EmulateLSLReg, "lsl{s}<c> <Rd>, <Rn>, <Rm>"},
13024 &EmulateInstructionARM::EmulateLSRImm, "lsr{s}<c> <Rd>, <Rm>, #imm"},
13027 &EmulateInstructionARM::EmulateLSRReg, "lsr{s}<c> <Rd>, <Rn>, <Rm>"},
13030 &EmulateInstructionARM::EmulateRRX, "rrx{s}<c> <Rd>, <Rm>"},
13033 &EmulateInstructionARM::EmulateRORImm, "ror{s}<c> <Rd>, <Rm>, #imm"},
13036 &EmulateInstructionARM::EmulateRORReg, "ror{s}<c> <Rd>, <Rn>, <Rm>"},
13039 &EmulateInstructionARM::EmulateMUL, "mul{s}<c> <Rd>,<R>,<Rm>"},
13130 &EmulateInstructionARM::EmulateSTREX, "strex<c> <Rd>, <Rt>, [<Rn>]"},
13160 &EmulateInstructionARM::EmulateSXTB, "sxtb<c> <Rd>,<Rm>{,<rotation>}"},
13162 &EmulateInstructionARM::EmulateSXTH, "sxth<c> <Rd>,<Rm>{,<rotation>}"},
13164 &EmulateInstructionARM::EmulateUXTB, "uxtb<c> <Rd>,<Rm>{,<rotation>}"},
13166 &EmulateInstructionARM::EmulateUXTH, "uxth<c> <Rd>,<Rm>{,<rotation>}"},
13222 "sub{s}<c> <Rd>, sp, <Rm>{,<shift>}"},
13233 &EmulateInstructionARM::EmulateADDSPImm, "add<c> <Rd>, sp, #imm"},
13304 &EmulateInstructionARM::EmulateADCImm, "adc{s}<c> <Rd>, <Rn>, #<const>"},
13310 "adc{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
13313 &EmulateInstructionARM::EmulateADDReg, "adds|add<c> <Rd>, <Rn>, <Rm>"},
13320 &EmulateInstructionARM::EmulateADR, "add<c> <Rd>, PC, #<const>"},
13322 &EmulateInstructionARM::EmulateADR, "sub<c> <Rd>, PC, #<const>"},
13324 &EmulateInstructionARM::EmulateADR, "add<c> <Rd>, PC, #<const>"},
13327 &EmulateInstructionARM::EmulateANDImm, "and{s}<c> <Rd>, <Rn>, #<const>"},
13333 "and{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
13336 &EmulateInstructionARM::EmulateBICImm, "bic{s}<c> <Rd>, <Rn>, #<const>"},
13342 "bic{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
13345 &EmulateInstructionARM::EmulateEORImm, "eor{s}<c> <Rd>, <Rn>, #<const>"},
13351 "eor{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
13354 &EmulateInstructionARM::EmulateORRImm, "orr{s}<c> <Rd>, <Rn>, #<const>"},
13360 "orr{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
13363 &EmulateInstructionARM::EmulateRSBImm, "rsbs|rsb<c> <Rd>, <Rn>, #0"},
13366 "rsb{s}<c>.w <Rd>, <Rn>, #<const>"},
13370 "rsb{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
13373 &EmulateInstructionARM::EmulateSBCImm, "sbc{s}<c> <Rd>, <Rn>, #<const>"},
13379 "sbc{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
13383 "adds|add<c> <Rd>,<Rn>,#<imm3>"},
13388 "add{s}<c>.w <Rd>,<Rn>,#<const>"},
13391 "addw<c> <Rd>,<Rn>,#<imm12>"},
13395 "subs|sub<c> <Rd>, <Rn> #imm3"},
13400 "sub{s}<c>.w <Rd>, <Rn>, #<const>"},
13403 "subw<c> <Rd>, <Rn>, #imm12"},
13406 &EmulateInstructionARM::EmulateSUBSPImm, "sub{s}.w <Rd>, sp, #<const>"},
13408 &EmulateInstructionARM::EmulateSUBSPImm, "subw<c> <Rd>, sp, #imm12"},
13411 &EmulateInstructionARM::EmulateSUBReg, "subs|sub<c> <Rd>, <Rn>, <Rm>"},
13414 "sub{s}<c>.w <Rd>, <Rn>, <Rm>{,<shift>}"},
13432 &EmulateInstructionARM::EmulateMOVRdRm, "mov<c> <Rd>, <Rm>"},
13435 &EmulateInstructionARM::EmulateMOVRdRm, "movs <Rd>, <Rm>"},
13436 // mov{s}<c>.w <Rd>, <Rm>
13438 &EmulateInstructionARM::EmulateMOVRdRm, "mov{s}<c>.w <Rd>, <Rm>"},
13441 &EmulateInstructionARM::EmulateMOVRdImm, "movs|mov<c> <Rd>, #imm8"},
13443 &EmulateInstructionARM::EmulateMOVRdImm, "mov{s}<c>.w <Rd>, #<const>"},
13445 &EmulateInstructionARM::EmulateMOVRdImm, "movw<c> <Rd>,#<imm16>"},
13448 &EmulateInstructionARM::EmulateMVNImm, "mvn{s} <Rd>, #<const>"},
13451 &EmulateInstructionARM::EmulateMVNReg, "mvns|mvn<c> <Rd>, <Rm>"},
13454 "mvn{s}<c>.w <Rd>, <Rm> {,<shift>}"},
13479 &EmulateInstructionARM::EmulateASRImm, "asrs|asr<c> <Rd>, <Rm>, #imm"},
13481 &EmulateInstructionARM::EmulateASRImm, "asr{s}<c>.w <Rd>, <Rm>, #imm"},
13486 &EmulateInstructionARM::EmulateASRReg, "asr{s}<c>.w <Rd>, <Rn>, <Rm>"},
13489 &EmulateInstructionARM::EmulateLSLImm, "lsls|lsl<c> <Rd>, <Rm>, #imm"},
13491 &EmulateInstructionARM::EmulateLSLImm, "lsl{s}<c>.w <Rd>, <Rm>, #imm"},
13496 &EmulateInstructionARM::EmulateLSLReg, "lsl{s}<c>.w <Rd>, <Rn>, <Rm>"},
13499 &EmulateInstructionARM::EmulateLSRImm, "lsrs|lsr<c> <Rd>, <Rm>, #imm"},
13501 &EmulateInstructionARM::EmulateLSRImm, "lsr{s}<c>.w <Rd>, <Rm>, #imm"},
13506 &EmulateInstructionARM::EmulateLSRReg, "lsr{s}<c>.w <Rd>, <Rn>, <Rm>"},
13509 &EmulateInstructionARM::EmulateRRX, "rrx{s}<c>.w <Rd>, <Rm>"},
13512 &EmulateInstructionARM::EmulateRORImm, "ror{s}<c>.w <Rd>, <Rm>, #imm"},
13517 &EmulateInstructionARM::EmulateRORReg, "ror{s}<c>.w <Rd>, <Rn>, <Rm>"},
13523 &EmulateInstructionARM::EmulateMUL, "mul<c> <Rd>,<Rn>,<Rm>"},
13684 "strex<c> <Rd>, <Rt>, [<Rn{,#<imm>}]"},
13705 &EmulateInstructionARM::EmulateSXTB, "sxtb<c> <Rd>,<Rm>"},
13707 &EmulateInstructionARM::EmulateSXTB, "sxtb<c>.w <Rd>,<Rm>{,<rotation>}"},
13709 &EmulateInstructionARM::EmulateSXTH, "sxth<c> <Rd>,<Rm>"},
13711 &EmulateInstructionARM::EmulateSXTH, "sxth<c>.w <Rd>,<Rm>{,<rotation>}"},
13713 &EmulateInstructionARM::EmulateUXTB, "uxtb<c> <Rd>,<Rm>"},
13715 &EmulateInstructionARM::EmulateUXTB, "uxtb<c>.w <Rd>,<Rm>{,<rotation>}"},
13717 &EmulateInstructionARM::EmulateUXTH, "uxth<c> <Rd>,<Rm>"},
13719 &EmulateInstructionARM::EmulateUXTH, "uxth<c>.w <Rd>,<Rm>{,<rotation>}"},
14197 // Write the result to the ARM core register Rd, and optionally update the
14216 Context &context, const uint32_t result, const uint32_t Rd, bool setflags,
14218 if (Rd == 15) {
14224 switch (Rd) {
14235 reg_num = dwarf_r0 + Rd;