| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 1235 Register RHSReg = getRegForValue(RHS); emitAddSub() local
1254 Register RHSReg = getRegForValue(MulLHS); emitAddSub() local
1277 Register RHSReg = getRegForValue(SI->getOperand(0)); emitAddSub() local
1289 Register RHSReg = getRegForValue(RHS); emitAddSub() local
1300 emitAddSub_rr(bool UseAdd,MVT RetVT,unsigned LHSReg,unsigned RHSReg,bool SetFlags,bool WantResult) emitAddSub_rr() argument
1382 emitAddSub_rs(bool UseAdd,MVT RetVT,unsigned LHSReg,unsigned RHSReg,AArch64_AM::ShiftExtendType ShiftType,uint64_t ShiftImm,bool SetFlags,bool WantResult) emitAddSub_rs() argument
1424 emitAddSub_rx(bool UseAdd,MVT RetVT,unsigned LHSReg,unsigned RHSReg,AArch64_AM::ShiftExtendType ExtType,uint64_t ShiftImm,bool SetFlags,bool WantResult) emitAddSub_rx() argument
1522 Register RHSReg = getRegForValue(RHS); emitFCmp() local
1569 emitSubs_rr(MVT RetVT,unsigned LHSReg,unsigned RHSReg,bool WantResult) emitSubs_rr() argument
1575 emitSubs_rs(MVT RetVT,unsigned LHSReg,unsigned RHSReg,AArch64_AM::ShiftExtendType ShiftType,uint64_t ShiftImm,bool WantResult) emitSubs_rs() argument
1624 Register RHSReg = getRegForValue(MulLHS); emitLogicalOp() local
1638 Register RHSReg = getRegForValue(SI->getOperand(0)); emitLogicalOp() local
1647 Register RHSReg = getRegForValue(RHS); emitLogicalOp() local
1706 emitLogicalOp_rs(unsigned ISDOpc,MVT RetVT,unsigned LHSReg,unsigned RHSReg,uint64_t ShiftImm) emitLogicalOp_rs() argument
3714 Register RHSReg = getRegForValue(RHS); fastLowerIntrinsicCall() local
3744 Register RHSReg = getRegForValue(RHS); fastLowerIntrinsicCall() local
3828 Register RHSReg = getRegForValue(II->getArgOperand(1)); fastLowerIntrinsicCall() local
[all...] |
| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 504 unsigned LHSReg, unsigned RHSReg, in validOpRegPair() argument
546 auto RHSReg = MIB.getReg(3); in selectCmp() local
578 insertComparison(CmpConstants Helper,InsertInfo I,unsigned ResReg,ARMCC::CondCodes Cond,unsigned LHSReg,unsigned RHSReg,unsigned PrevRes) const insertComparison() argument
[all...] |
| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 2130 Register RHSReg = getRegForValue(RHS); X86FastEmitCMoveSelect() local
2187 Register RHSReg = getRegForValue(RHS); X86FastEmitSSESelect() local
2332 Register RHSReg = getRegForValue(RHS); X86FastEmitPseudoSelect() local
2912 unsigned RHSReg; fastLowerIntrinsicCall() local
3073 Register RHSReg = getRegForValue(RHS); fastLowerIntrinsicCall() local
[all...] |
| /llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 3119 Register RHSReg = MI.getOperand(2).getReg(); matchHoistLogicOpWithSameOpcodeHands() local
4777 Register RHSReg = MI.getOffsetReg(); matchReassocConstantInnerLHS() local
4899 Register RHSReg = MI.getOperand(2).getReg(); matchReassocCommBinOp() local
6027 Register RHSReg = MI.getOperand(2).getReg(); matchCombineFSubFNegFMulToFMadOrFMA() local
6074 Register RHSReg = MI.getOperand(2).getReg(); matchCombineFSubFpExtFMulToFMadOrFMA() local
6127 Register RHSReg = MI.getOperand(2).getReg(); matchCombineFSubFpExtFNegFMulToFMadOrFMA() local
6519 Register RHSReg = MI.getOperand(RHSOpndIdx).getReg(); applyCommuteBinOpOperands() local
[all...] |
| /llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 316 RHSReg = materializeInt(C, MVT::i32); in emitLogicalOp() local
|