Lines Matching defs:RHSReg
207 unsigned RHSReg, bool SetFlags = false,
213 unsigned RHSReg, AArch64_AM::ShiftExtendType ShiftType,
217 unsigned RHSReg, AArch64_AM::ShiftExtendType ExtType,
242 unsigned emitSubs_rr(MVT RetVT, unsigned LHSReg, unsigned RHSReg,
244 unsigned emitSubs_rs(MVT RetVT, unsigned LHSReg, unsigned RHSReg,
252 unsigned RHSReg, uint64_t ShiftImm);
1237 Register RHSReg = getRegForValue(RHS);
1238 if (!RHSReg)
1240 return emitAddSub_rx(UseAdd, RetVT, LHSReg, RHSReg, ExtendType, 0,
1256 Register RHSReg = getRegForValue(MulLHS);
1257 if (!RHSReg)
1259 ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, RHSReg, AArch64_AM::LSL,
1279 Register RHSReg = getRegForValue(SI->getOperand(0));
1280 if (!RHSReg)
1282 ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, RHSReg, ShiftType,
1291 Register RHSReg = getRegForValue(RHS);
1292 if (!RHSReg)
1296 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt);
1298 return emitAddSub_rr(UseAdd, RetVT, LHSReg, RHSReg, SetFlags, WantResult);
1302 unsigned RHSReg, bool SetFlags,
1304 assert(LHSReg && RHSReg && "Invalid register number.");
1307 RHSReg == AArch64::SP || RHSReg == AArch64::WSP)
1331 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);
1334 .addReg(RHSReg);
1384 unsigned RHSReg,
1388 assert(LHSReg && RHSReg && "Invalid register number.");
1390 RHSReg != AArch64::SP && RHSReg != AArch64::WSP);
1417 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);
1420 .addReg(RHSReg)
1426 unsigned RHSReg,
1430 assert(LHSReg && RHSReg && "Invalid register number.");
1432 RHSReg != AArch64::XZR && RHSReg != AArch64::WZR);
1461 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);
1464 .addReg(RHSReg)
1524 Register RHSReg = getRegForValue(RHS);
1525 if (!RHSReg)
1531 .addReg(RHSReg);
1571 unsigned RHSReg, bool WantResult) {
1572 return emitAddSub_rr(/*UseAdd=*/false, RetVT, LHSReg, RHSReg,
1577 unsigned RHSReg,
1580 return emitAddSub_rs(/*UseAdd=*/false, RetVT, LHSReg, RHSReg, ShiftType,
1626 Register RHSReg = getRegForValue(MulLHS);
1627 if (!RHSReg)
1629 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, RHSReg, ShiftVal);
1640 Register RHSReg = getRegForValue(SI->getOperand(0));
1641 if (!RHSReg)
1643 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, RHSReg, ShiftVal);
1649 Register RHSReg = getRegForValue(RHS);
1650 if (!RHSReg)
1654 ResultReg = fastEmit_rr(VT, VT, ISDOpc, LHSReg, RHSReg);
1708 unsigned LHSReg, unsigned RHSReg,
1740 fastEmitInst_rri(Opc, RC, LHSReg, RHSReg,
3720 Register RHSReg = getRegForValue(RHS);
3721 if (!RHSReg)
3725 MulReg = emitSMULL_rr(MVT::i64, LHSReg, RHSReg);
3735 // LHSReg and RHSReg cannot be killed by this Mul, since they are
3737 MulReg = emitMul_rr(VT, LHSReg, RHSReg);
3738 unsigned SMULHReg = fastEmit_rr(VT, VT, ISD::MULHS, LHSReg, RHSReg);
3750 Register RHSReg = getRegForValue(RHS);
3751 if (!RHSReg)
3755 MulReg = emitUMULL_rr(MVT::i64, LHSReg, RHSReg);
3764 // LHSReg and RHSReg cannot be killed by this Mul, since they are
3766 MulReg = emitMul_rr(VT, LHSReg, RHSReg);
3767 unsigned UMULHReg = fastEmit_rr(VT, VT, ISD::MULHU, LHSReg, RHSReg);
3834 Register RHSReg = getRegForValue(II->getArgOperand(1));
3835 if (!LHSReg || !RHSReg)
3839 fastEmitInst_rr(Opc, &AArch64::GPR32RegClass, LHSReg, RHSReg);