Searched defs:RCID (Results 1 – 10 of 10) sorted by relevance
203 isSGPRClassID(unsigned RCID) isSGPRClassID() argument
5549 adjustAllocatableRegClass(const GCNSubtarget & ST,const SIRegisterInfo & RI,const MachineRegisterInfo & MRI,const MCInstrDesc & TID,unsigned RCID,bool IsAllocatable) adjustAllocatableRegClass() argument 5625 unsigned RCID = Desc.operands()[OpNo].RegClass; getOpRegClass() local 5634 unsigned RCID = get(MI.getOpcode()).operands()[OpIdx].RegClass; legalizeOpWithMove() local 9029 const auto RCID = MI.getDesc().operands()[Idx].RegClass; isBufferSMRD() local [all...]
378 unsigned RCID = N->getConstantOperandVal(0); getOperandRegClass() local
809 int RCID = Desc.operands()[OpNo].RegClass; printRegularOperand() local 895 int RCID = Desc.operands()[OpNo].RegClass; printRegularOperand() local
1596 unsigned RCID; handleSpecialFP() local
970 unsigned RCID; getRegClassConstraint() local 1837 unsigned RCID; print() local
1766 unsigned RCID; createMIROperandComment() local
272 return isRegClass(RCID) || isInlinableImm(type); in isRegOrInline() argument 276 return isRegOrInline(RCID, type) || isLiteralImm(type); in isRegOrImmWithInputMods() argument 416 isRegOrInlineNoMods(unsigned RCID,MVT type) const isRegOrInlineNoMods() argument 2820 int RCID = getRegClass(RegKind, RegWidth); getRegularReg() local [all...]
2403 getRegBitWidth(unsigned RCID) getRegBitWidth() argument 2549 unsigned RCID = Desc.operands()[OpNo].RegClass; getRegOperandSize() local
216 unsigned RCID = getRegClassIDForVecVT(ContainerVT); RISCVTargetLowering() local