Lines Matching defs:RCID

5709                           const MCInstrDesc &TID, unsigned RCID,
5715     switch (RCID) {
5717       RCID = AMDGPU::VGPR_32RegClassID;
5720       RCID = AMDGPU::VReg_64RegClassID;
5723       RCID = AMDGPU::VReg_96RegClassID;
5726       RCID = AMDGPU::VReg_128RegClassID;
5729       RCID = AMDGPU::VReg_160RegClassID;
5732       RCID = AMDGPU::VReg_512RegClassID;
5739   return RI.getProperlyAlignedRC(RI.getRegClass(RCID));
5785   unsigned RCID = Desc.operands()[OpNo].RegClass;
5786   return adjustAllocatableRegClass(ST, RI, MRI, Desc, RCID, true);
5794   unsigned RCID = get(MI.getOpcode()).operands()[OpIdx].RegClass;
5795   const TargetRegisterClass *RC = RI.getRegClass(RCID);
9198   const auto RCID = MI.getDesc().operands()[Idx].RegClass;
9199   return RI.getRegClass(RCID)->hasSubClassEq(&AMDGPU::SGPR_128RegClass);