| /llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | RegisterClassInfo.h | 79 const RCInfo &RCI = RegClass[RC->getID()]; in get() local
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| H A D | RegisterPressure.h | 362 const RegisterClassInfo *RCI = nullptr; global() variable
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| /llvm-project/llvm/lib/CodeGen/ |
| H A D | RegisterClassInfo.cpp | 127 RCInfo &RCI = RegClass[RC->getID()]; compute() local
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| H A D | CriticalAntiDepBreaker.cpp | 42 const RegisterClassInfo &RCI) in CriticalAntiDepBreaker() argument
696 const RegisterClassInfo &RCI) { in createCriticalAntiDepBreaker() argument
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| H A D | AggressiveAntiDepBreaker.cpp | 121 MachineFunction &MFi, const RegisterClassInfo &RCI, in AggressiveAntiDepBreaker() argument
964 createAggressiveAntiDepBreaker(MachineFunction & MFi,const RegisterClassInfo & RCI,TargetSubtargetInfo::RegClassVector & CriticalPathRCs) createAggressiveAntiDepBreaker() argument
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| H A D | PostRASchedulerList.cpp | 204 SchedulePostRATDList(MachineFunction & MF,MachineLoopInfo & MLI,AliasAnalysis * AA,const RegisterClassInfo & RCI,TargetSubtargetInfo::AntiDepBreakMode AntiDepMode,SmallVectorImpl<const TargetRegisterClass * > & CriticalPathRCs) SchedulePostRATDList() argument
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| H A D | ShrinkWrap.cpp | 116 RegisterClassInfo RCI; global() member in __anon326b4ad00111::ShrinkWrap
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| H A D | TargetRegisterInfo.cpp | 307 for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI) getMatchingSuperRegClass() local
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| H A D | RegisterPressure.cpp | 954 computeExcessPressureDelta(ArrayRef<unsigned> OldPressureVec,ArrayRef<unsigned> NewPressureVec,RegPressureDelta & Delta,const RegisterClassInfo * RCI,ArrayRef<unsigned> LiveThruPressureVec) computeExcessPressureDelta() argument
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| H A D | MachinePipeliner.cpp | 1320 computePressureSetLimit(const RegisterClassInfo & RCI) computePressureSetLimit() argument
1530 init(const RegisterClassInfo & RCI) init() argument
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| H A D | TargetLoweringBase.cpp | 1421 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI) findRepresentativeClass() local
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| H A D | RegAllocGreedy.cpp | 1341 getNumAllocatableRegsForConstraints(const MachineInstr * MI,Register Reg,const TargetRegisterClass * SuperRC,const TargetInstrInfo * TII,const TargetRegisterInfo * TRI,const RegisterClassInfo & RCI) getNumAllocatableRegsForConstraints() argument
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| /llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | ConstantHoisting.cpp | 167 for (const RebasedConstantInfo &RCI : RebasedConstants) collectMatInsertPts() local
869 for (auto const &RCI : ConstInfo.RebasedConstants) { emitBaseConstants() local
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| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNRewritePartialRegUses.cpp | 192 I->second = RCI.getMask(); in getSuperRegClassMask() local
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| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64A57FPLoadBalancing.cpp | 111 RegisterClassInfo RCI; member in __anondfbe7f5c0111::AArch64A57FPLoadBalancing
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