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Searched defs:PredReg (Results 1 – 21 of 21) sorted by relevance

/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb2InstrInfo.cpp73 Register PredReg; ReplaceTailWithBranchTo() local
121 Register PredReg; isLegalToSplitMBBAt() local
293 emitT2RegPlusImmediate(MachineBasicBlock & MBB,MachineBasicBlock::iterator & MBBI,const DebugLoc & dl,Register DestReg,Register BaseReg,int NumBytes,ARMCC::CondCodes Pred,Register PredReg,const ARMBaseInstrInfo & TII,unsigned MIFlags) emitT2RegPlusImmediate() argument
553 Register PredReg; rewriteT2FrameIndex() local
767 getITInstrPredicate(const MachineInstr & MI,Register & PredReg) getITInstrPredicate() argument
785 getVPTInstrPredicate(const MachineInstr & MI,Register & PredReg) getVPTInstrPredicate() argument
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H A DThumb2InstrInfo.h86 Register PredReg; getVPTInstrPredicate() local
H A DARMLoadStoreOptimizer.cpp490 unsigned PredReg) { in UpdateBaseRegUses() argument
630 CreateLoadStoreMulti(MachineBasicBlock & MBB,MachineBasicBlock::iterator InsertBefore,int Offset,unsigned Base,bool BaseKill,unsigned Opcode,ARMCC::CondCodes Pred,unsigned PredReg,const DebugLoc & DL,ArrayRef<std::pair<unsigned,bool>> Regs,ArrayRef<MachineInstr * > Instrs) CreateLoadStoreMulti() argument
837 CreateLoadStoreDouble(MachineBasicBlock & MBB,MachineBasicBlock::iterator InsertBefore,int Offset,unsigned Base,bool BaseKill,unsigned Opcode,ARMCC::CondCodes Pred,unsigned PredReg,const DebugLoc & DL,ArrayRef<std::pair<unsigned,bool>> Regs,ArrayRef<MachineInstr * > Instrs) const CreateLoadStoreDouble() argument
907 Register PredReg; MergeOpsUpdate() local
1191 isIncrementOrDecrement(const MachineInstr & MI,Register Reg,ARMCC::CondCodes Pred,Register PredReg) isIncrementOrDecrement() argument
1223 findIncDecBefore(MachineBasicBlock::iterator MBBI,Register Reg,ARMCC::CondCodes Pred,Register PredReg,int & Offset) findIncDecBefore() argument
1243 findIncDecAfter(MachineBasicBlock::iterator MBBI,Register Reg,ARMCC::CondCodes Pred,Register PredReg,int & Offset,const TargetRegisterInfo * TRI) findIncDecAfter() argument
1296 Register PredReg; MergeBaseUpdateLSMultiple() local
1492 Register PredReg; MergeBaseUpdateLoadStore() local
1630 Register PredReg; MergeBaseUpdateLSDouble() local
1737 InsertLDR_STR(MachineBasicBlock & MBB,MachineBasicBlock::iterator & MBBI,int Offset,bool isDef,unsigned NewOpc,unsigned Reg,bool RegDeadKill,bool RegUndef,unsigned BaseReg,bool BaseKill,bool BaseUndef,ARMCC::CondCodes Pred,unsigned PredReg,const TargetInstrInfo * TII,MachineInstr * MI) InsertLDR_STR() argument
1800 Register PredReg; FixInvalidRegPairOp() local
1900 Register PredReg; LoadStoreMultipleOpti() local
2256 CanFormLdStDWord(MachineInstr * Op0,MachineInstr * Op1,DebugLoc & dl,unsigned & NewOpc,Register & FirstReg,Register & SecondReg,Register & BaseReg,int & Offset,Register & PredReg,ARMCC::CondCodes & Pred,bool & isT2) CanFormLdStDWord() argument
2415 Register BaseReg, PredReg; RescheduleOps() local
2564 Register PredReg; RescheduleLoadStoreInstrs() local
3178 Register PredReg; DistributeIncrements() local
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H A DMVEVPTBlockPass.cpp105 Register PredReg; in StepOverPredicatedInstrs() local
250 Register PredReg; InsertVPTBlocks() local
H A DThumb2SizeReduction.cpp469 Register PredReg = MI->getOperand(5).getReg(); in ReduceLoadStore() local
687 Register PredReg; in ReduceSpecial() local
729 Register PredReg; in ReduceSpecial() local
800 Register PredReg; in ReduceTo2Addr() local
892 Register PredReg; in ReduceToNarrow() local
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H A DThumbRegisterInfo.cpp65 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb1LoadConstPool()
85 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb2LoadConstPool()
106 ARMCC::CondCodes Pred, Register PredReg, unsigned MIFlags) const { in emitLoadConstPool()
H A DThumb2ITBlockPass.cpp201 Register PredReg; in InsertITInstructions() local
H A DARMBaseRegisterInfo.cpp499 ARMCC::CondCodes Pred, Register PredReg, unsigned MIFlags) const { in emitLoadConstPool() argument
852 Register PredReg = (PIdx == -1) ? Register() : MI.getOperand(PIdx+1).getReg(); in eliminateFrameIndex() local
H A DARMConstantIslandPass.cpp1470 Register PredReg; in createNewWater() local
1516 Register PredReg; in createNewWater() local
1540 Register PredReg; in createNewWater() local
1943 Register PredReg; in optimizeThumb2Branches() local
H A DMLxExpansionPass.cpp282 Register PredReg = MI->getOperand(++NextOp).getReg(); in ExpandFPMLxInstruction() local
H A DARMFrameLowering.cpp538 emitRegPlusImmediate(bool isARM,MachineBasicBlock & MBB,MachineBasicBlock::iterator & MBBI,const DebugLoc & dl,const ARMBaseInstrInfo & TII,unsigned DestReg,unsigned SrcReg,int NumBytes,unsigned MIFlags=MachineInstr::NoFlags,ARMCC::CondCodes Pred=ARMCC::AL,unsigned PredReg=0) emitRegPlusImmediate() argument
552 emitSPUpdate(bool isARM,MachineBasicBlock & MBB,MachineBasicBlock::iterator & MBBI,const DebugLoc & dl,const ARMBaseInstrInfo & TII,int NumBytes,unsigned MIFlags=MachineInstr::NoFlags,ARMCC::CondCodes Pred=ARMCC::AL,unsigned PredReg=0) emitSPUpdate() argument
2886 unsigned PredReg = TII.getFramePred(*I); eliminateCallFramePseudoInstr() local
H A DARMISelDAGToDAG.cpp1752 SDValue PredReg; tryMVEIndexedLoad() local
2919 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); SelectCDE_CXxD() local
4273 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); Select() local
4285 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); Select() local
4296 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); Select() local
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H A DARMBaseInstrInfo.cpp2233 getInstrPredicate(const MachineInstr & MI,Register & PredReg) getInstrPredicate() argument
2263 Register PredReg; commuteInstructionImpl() local
2471 emitARMRegPlusImmediate(MachineBasicBlock & MBB,MachineBasicBlock::iterator & MBBI,const DebugLoc & dl,Register DestReg,Register BaseReg,int NumBytes,ARMCC::CondCodes Pred,Register PredReg,const ARMBaseInstrInfo & TII,unsigned MIFlags) emitARMRegPlusImmediate() argument
5617 Register PredReg; findCMPToFoldIntoCBZ() local
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H A DARMExpandPseudoInsts.cpp1066 Register PredReg; ExpandMOV32BitImm() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp190 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
H A DHexagonMCCompound.cpp177 unsigned PredReg = Predicate.getReg(); in getCompoundOp() local
H A DHexagonMCChecker.cpp68 void HexagonMCChecker::initReg(MCInst const &MCI, unsigned R, unsigned &PredReg, in initReg()
94 unsigned PredReg = Hexagon::NoRegister; in init() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenPredicate.cpp321 bool HexagonGenPredicate::isScalarPred(RegisterSubReg PredReg) { in isScalarPred() argument
H A DHexagonInstrInfo.cpp1700 Register PredReg; PredicateInstruction() local
4521 getPredReg(ArrayRef<MachineOperand> Cond,Register & PredReg,unsigned & PredRegPos,unsigned & PredRegFlags) const getPredReg() argument
H A DHexagonHardwareLoops.cpp651 Register PredReg; in getLoopTripCount() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp1357 optimizePTestInstr(MachineInstr * PTest,unsigned MaskReg,unsigned PredReg,const MachineRegisterInfo * MRI) const optimizePTestInstr() argument