Lines Matching defs:PredReg
175 ARMCC::CondCodes Pred, unsigned PredReg);
179 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
185 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
490 unsigned PredReg) {
559 .addReg(PredReg);
581 .addReg(PredReg);
631 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
751 .add(predOps(Pred, PredReg));
762 .add(predOps(Pred, PredReg));
768 .add(predOps(Pred, PredReg));
773 .add(predOps(Pred, PredReg))
818 UpdateBaseRegUses(MBB, InsertBefore, DL, Base, NumRegs, Pred, PredReg);
825 MIB.addImm(Pred).addReg(PredReg);
838 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
855 MIB.addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
908 Register PredReg;
909 ARMCC::CondCodes Pred = getInstrPredicate(*First, PredReg);
914 Opcode, Pred, PredReg, DL, Regs,
918 Opcode, Pred, PredReg, DL, Regs, Cand.Instrs);
1192 ARMCC::CondCodes Pred, Register PredReg) {
1213 MIPredReg != PredReg)
1224 ARMCC::CondCodes Pred, Register PredReg, int &Offset) {
1237 Offset = isIncrementOrDecrement(*PrevMBBI, Reg, Pred, PredReg);
1244 ARMCC::CondCodes Pred, Register PredReg, int &Offset,
1257 unsigned Off = isIncrementOrDecrement(*NextMBBI, Reg, Pred, PredReg);
1297 Register PredReg;
1298 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
1313 = findIncDecBefore(MBBI, Base, Pred, PredReg, Offset);
1320 MergeInstr = findIncDecAfter(MBBI, Base, Pred, PredReg, Offset, TRI);
1353 .addImm(Pred).addReg(PredReg);
1493 Register PredReg;
1494 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
1500 = findIncDecBefore(MBBI, Base, Pred, PredReg, Offset);
1507 MergeInstr = findIncDecAfter(MBBI, Base, Pred, PredReg, Offset, TRI);
1535 .addReg(PredReg)
1551 .addReg(PredReg)
1563 .add(predOps(Pred, PredReg))
1575 .add(predOps(Pred, PredReg))
1593 .add(predOps(Pred, PredReg))
1603 .add(predOps(Pred, PredReg))
1631 Register PredReg;
1632 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
1637 PredReg, Offset);
1642 MergeInstr = findIncDecAfter(MBBI, Base, Pred, PredReg, Offset, TRI);
1661 .addImm(Offset).addImm(Pred).addReg(PredReg);
1738 unsigned PredReg, const TargetInstrInfo *TII,
1745 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1754 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1801 Register PredReg;
1802 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
1813 .addImm(Pred).addReg(PredReg)
1821 .addImm(Pred).addReg(PredReg)
1844 false, BaseReg, false, BaseUndef, Pred, PredReg, TII, MI);
1846 false, BaseReg, BaseKill, BaseUndef, Pred, PredReg, TII,
1860 EvenUndef, BaseReg, false, BaseUndef, Pred, PredReg, TII,
1863 OddUndef, BaseReg, BaseKill, BaseUndef, Pred, PredReg, TII,
1901 Register PredReg;
1902 ARMCC::CondCodes Pred = getInstrPredicate(*MBBI, PredReg);
1912 // Note: No need to match PredReg in the next if.
2172 Register &BaseReg, int &Offset, Register &PredReg,
2258 Register &PredReg, ARMCC::CondCodes &Pred, bool &isT2) {
2318 Pred = getInstrPredicate(*Op0, PredReg);
2417 Register BaseReg, PredReg;
2425 Offset, PredReg, Pred, isT2)) {
2445 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
2459 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
2566 Register PredReg;
2567 if (getInstrPredicate(MI, PredReg) != ARMCC::AL)
3180 Register PredReg;
3182 getInstrPredicate(*Increment, PredReg) != ARMCC::AL)