Searched defs:PhiReg (Results 1 – 4 of 4) sorted by relevance
| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | MVETPAndVPTOptimisationsPass.cpp | 356 Register PhiReg = LoopPhi->getOperand(0).getReg(); MergeLoopEnd() local
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| /llvm-project/llvm/lib/CodeGen/ |
| H A D | ModuloSchedule.cpp | 1679 Register PhiReg = MI.getOperand(0).getReg(); moveStageBetweenBlocks() local
2436 Register PhiReg = MRI.createVirtualRegister(MRI.getRegClass(OrigReg)); generatePhi() local
2479 Register PhiReg = MRI.createVirtualRegister(MRI.getRegClass(OrigReg)); mergeRegUsesAfterPipeline() local
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| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonHardwareLoops.cpp | 1622 MachineInstr *DI = MRI->getVRegDef(PhiReg); in fixupInductionVariable() local
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| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 4450 emitLoadM0FromVGPRLoop(const SIInstrInfo * TII,MachineRegisterInfo & MRI,MachineBasicBlock & OrigBB,MachineBasicBlock & LoopBB,const DebugLoc & DL,const MachineOperand & Idx,unsigned InitReg,unsigned ResultReg,unsigned PhiReg,unsigned InitSaveExecReg,int Offset,bool UseGPRIdxMode,Register & SGPRIdxReg) emitLoadM0FromVGPRLoop() argument
4540 loadM0FromVGPR(const SIInstrInfo * TII,MachineBasicBlock & MBB,MachineInstr & MI,unsigned InitResultReg,unsigned PhiReg,int Offset,bool UseGPRIdxMode,Register & SGPRIdxReg) loadM0FromVGPR() argument
4697 Register PhiReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); emitIndirectSrc() local
4802 Register PhiReg = MRI.createVirtualRegister(VecRC); emitIndirectDst() local
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