| /llvm-project/llvm/unittests/CodeGen/ |
| H A D | AllocationOrderTest.cpp | 29 SmallVector<MCPhysReg, 16> Order = {4, 5, 6, 7}; in TEST() local
36 SmallVector<MCPhysReg, 16> Order = {4, 1, 5, 6}; in TEST() local
43 SmallVector<MCPhysReg, 16> Order = {4, 5, 6, 7}; in TEST() local
50 SmallVector<MCPhysReg, 16> Order = {4, 5, 6, 7}; in TEST() local
59 SmallVector<MCPhysReg, 16> Order = {4, 1, 5, 6}; in TEST() local
69 SmallVector<MCPhysReg, 16> Order = {4, 1, 5, 6}; in TEST() local
76 SmallVector<MCPhysReg, 16> Order = {1, 4, 5, 6}; in TEST() local
83 SmallVector<MCPhysReg, 16> Order = {1, 4, 5, 6}; in TEST() local
92 SmallVector<MCPhysReg, 16> Order = {1, 2, 3, 4}; in TEST() local
101 SmallVector<MCPhysReg, 16> Order = {4, 1, 5, 6}; in TEST() local
|
| /llvm-project/llvm/unittests/Transforms/Utils/ |
| H A D | CodeLayoutTest.cpp | 18 auto Order = computeCacheDirectedLayout(Sizes, Counts, Edges, CallOffsets); in TEST() local
28 auto Order = computeCacheDirectedLayout(Sizes, Counts, Edges, CallOffsets); in TEST() local
41 auto Order = computeCacheDirectedLayout(Sizes, Counts, Edges, CallOffsets); in TEST() local
62 auto Order = computeCacheDirectedLayout(Sizes, Counts, Edges, CallOffsets); in TEST() local
|
| /llvm-project/llvm/tools/llvm-readtapi/ |
| H A D | DiffEngine.cpp | 26 StringRef setOrderIndicator(InterfaceInputOrder Order) { in setOrderIndicator()
128 InterfaceInputOrder Order) { in addDiffForTargSlice()
147 std::string Name, InterfaceInputOrder Order) { in getSingleAttrDiff()
160 std::string Name, InterfaceInputOrder Order) { in getSingleAttrDiff()
171 std::string Name, InterfaceInputOrder Order) { in getSingleAttrDiff()
196 const T &Val, InterfaceInputOrder Order) { in diffAttribute()
201 InterfaceInputOrder Order) { in getSingleIF()
239 DiffOutput &Result, InterfaceInputOrder Order) { in findAndAddDiff()
257 DiffOutput &Result, InterfaceInputOrder Order) { in findAndAddDiff()
270 DiffOutput &Result, InterfaceInputOrder Order) { in findAndAddDiff()
|
| H A D | DiffEngine.h | 64 DiffScalarVal(InterfaceInputOrder Order, T Val) in DiffScalarVal()
83 SymScalar(InterfaceInputOrder Order, const MachO::Symbol *Sym) in SymScalar()
|
| /llvm-project/llvm/lib/CodeGen/ |
| H A D | AllocationOrder.h | 32 ArrayRef<MCPhysReg> Order; variable
90 AllocationOrder(SmallVector<MCPhysReg, 16> &&Hints, ArrayRef<MCPhysReg> Order, in AllocationOrder()
|
| H A D | AllocationOrder.cpp | 34 auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); in create() local
|
| H A D | RegAllocGreedy.cpp | 400 tryAssign(const LiveInterval & VirtReg,AllocationOrder & Order,SmallVectorImpl<Register> & NewVRegs,const SmallVirtRegSet & FixedRegisters) tryAssign() argument
534 getOrderLimit(const LiveInterval & VirtReg,const AllocationOrder & Order,unsigned CostPerUseLimit) const getOrderLimit() argument
580 tryEvict(const LiveInterval & VirtReg,AllocationOrder & Order,SmallVectorImpl<Register> & NewVRegs,uint8_t CostPerUseLimit,const SmallVirtRegSet & FixedRegisters) tryEvict() argument
871 calcGlobalSplitCost(GlobalSplitCandidate & Cand,const AllocationOrder & Order) calcGlobalSplitCost() argument
1063 tryRegionSplit(const LiveInterval & VirtReg,AllocationOrder & Order,SmallVectorImpl<Register> & NewVRegs) tryRegionSplit() argument
1097 calculateRegionSplitCostAroundReg(MCPhysReg PhysReg,AllocationOrder & Order,BlockFrequency & BestCost,unsigned & NumCands,unsigned & BestCand) calculateRegionSplitCostAroundReg() argument
1174 calculateRegionSplitCost(const LiveInterval & VirtReg,AllocationOrder & Order,BlockFrequency & BestCost,unsigned & NumCands,bool IgnoreCSR) calculateRegionSplitCost() argument
1236 trySplitAroundHintReg(MCPhysReg Hint,const LiveInterval & VirtReg,SmallVectorImpl<Register> & NewVRegs,AllocationOrder & Order) trySplitAroundHintReg() argument
1296 tryBlockSplit(const LiveInterval & VirtReg,AllocationOrder & Order,SmallVectorImpl<Register> & NewVRegs) tryBlockSplit() argument
1417 tryInstructionSplit(const LiveInterval & VirtReg,AllocationOrder & Order,SmallVectorImpl<Register> & NewVRegs) tryInstructionSplit() argument
1570 tryLocalSplit(const LiveInterval & VirtReg,AllocationOrder & Order,SmallVectorImpl<Register> & NewVRegs) tryLocalSplit() argument
1800 trySplit(const LiveInterval & VirtReg,AllocationOrder & Order,SmallVectorImpl<Register> & NewVRegs,const SmallVirtRegSet & FixedRegisters) trySplit() argument
1957 tryLastChanceRecoloring(const LiveInterval & VirtReg,AllocationOrder & Order,SmallVectorImpl<Register> & NewVRegs,SmallVirtRegSet & FixedRegisters,RecoloringStack & RecolorStack,unsigned Depth) tryLastChanceRecoloring() argument
2177 tryAssignCSRFirstTime(const LiveInterval & VirtReg,AllocationOrder & Order,MCRegister PhysReg,uint8_t & CostPerUseLimit,SmallVectorImpl<Register> & NewVRegs) tryAssignCSRFirstTime() argument
2417 auto Order = selectOrSplitImpl() local
[all...] |
| H A D | LocalStackSlotAllocation.cpp | 59 unsigned Order; member in __anon84125d900111::FrameRef
323 unsigned Order = 0; in insertFrameReferenceRegisters() local
|
| H A D | RegAllocBasic.cpp | 263 auto Order = selectOrSplit() local
|
| H A D | BreakFalseDeps.cpp | 156 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC); in pickBestRegisterForUndef() local
|
| H A D | RegAllocEvictionAdvisor.cpp | 277 const LiveInterval &VirtReg, const AllocationOrder &Order, in tryFindEvictionCandidate() argument
|
| H A D | TargetRegisterInfo.cpp | 248 ArrayRef<MCPhysReg> Order = RC->getRawAllocationOrder(MF); getAllocatableSetForRC() local
420 getRegAllocationHints(Register VirtReg,ArrayRef<MCPhysReg> Order,SmallVectorImpl<MCPhysReg> & Hints,const MachineFunction & MF,const VirtRegMap * VRM,const LiveRegMatrix * Matrix) const getRegAllocationHints() argument
|
| /llvm-project/bolt/lib/Passes/ |
| H A D | ReorderData.cpp | 163 DataOrder Order; in baseOrder() local
273 DataOrder Order = baseOrder(BC, Section); in sortedByFunc() local
305 DataOrder Order = baseOrder(BC, Section); in sortedByCount() local
483 DataOrder Order; in runOnFunctions() local
|
| /llvm-project/clang-tools-extra/clangd/unittests/ |
| H A D | ThreadCrashReporterTests.cpp | 59 std::string Order = ""; in TEST() local
|
| /llvm-project/llvm/lib/Support/ |
| H A D | DynamicLibrary.cpp | 81 void *LibLookup(const char *Symbol, DynamicLibrary::SearchOrdering Order) { in LibLookup()
96 void *Lookup(const char *Symbol, DynamicLibrary::SearchOrdering Order) { in Lookup()
|
| /llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SDNodeDbgValue.h | 149 unsigned Order; variable
245 unsigned Order; variable
|
| H A D | ScheduleDAGSDNodes.cpp | 740 InstrEmitter::VRBaseMapType &VRBaseMap, unsigned Order) { in ProcessSDDbgValues() argument
788 unsigned Order = N->getIROrder(); in ProcessSourceNode() local
992 unsigned Order = Orders[i].first; EmitSchedule() local
1038 unsigned Order = InstrOrder.first; EmitSchedule() local
[all...] |
| /llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | RegisterClassInfo.h | 36 std::unique_ptr<MCPhysReg[]> Order; member
|
| /llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZRegisterInfo.cpp | 57 static void addHints(ArrayRef<MCPhysReg> Order, in addHints() argument
75 Register VirtReg, ArrayRef<MCPhysReg> Order, in getRegAllocationHints() argument
|
| /llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenRegisters.h | 569 unsigned Order = 0; // Cache the sort key. global() member
803 getRegSetIDAt(unsigned Order) getRegSetIDAt() argument
807 getRegSetAt(unsigned Order) getRegSetAt() argument
|
| /llvm-project/llvm/tools/llvm-profgen/ |
| H A D | CSPreInliner.cpp | 78 std::vector<FunctionId> Order; in buildTopDownOrder() local
|
| /llvm-project/bolt/lib/Profile/ |
| H A D | YAMLProfileWriter.cpp | 73 BinaryFunction::BasicBlockOrderType Order; convert() local
|
| /llvm-project/llvm/include/llvm/Frontend/OpenMP/ |
| H A D | OMPIRBuilder.h | 246 OffloadEntryInfo(OffloadingEntryInfoKinds Kind,unsigned Order,uint32_t Flags) OffloadEntryInfo() argument
272 unsigned Order = ~0u; global() variable
302 OffloadEntryInfoTargetRegion(unsigned Order,Constant * Addr,Constant * ID,OMPTargetRegionEntryKind Flags) OffloadEntryInfoTargetRegion() argument
390 OffloadEntryInfoDeviceGlobalVar(unsigned Order,OMPTargetGlobalVarEntryKind Flags) OffloadEntryInfoDeviceGlobalVar() argument
393 OffloadEntryInfoDeviceGlobalVar(unsigned Order,Constant * Addr,int64_t VarSize,OMPTargetGlobalVarEntryKind Flags,GlobalValue::LinkageTypes Linkage,const std::string & VarName) OffloadEntryInfoDeviceGlobalVar() argument
[all...] |
| /llvm-project/bolt/lib/Core/ |
| H A D | BinarySection.cpp | 242 reorderContents(const std::vector<BinaryData * > & Order,bool Inplace) reorderContents() argument
|
| /llvm-project/libcxx/benchmarks/algorithms/ |
| H A D | common.h | |