Lines Matching defs:Order
401 AllocationOrder &Order,
405 for (auto I = Order.begin(), E = Order.end(); I != E && !PhysReg; ++I) {
422 if (Order.isHint(Hint)) {
433 if (trySplitAroundHintReg(PhysHint, VirtReg, NewVRegs, Order))
450 MCRegister CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost, FixedRegisters);
535 const AllocationOrder &Order,
537 unsigned OrderLimit = Order.getOrder().size();
551 if (RegCosts[Order.getOrder().back()] >= CostPerUseLimit) {
578 /// @param Order Physregs to try.
581 AllocationOrder &Order,
589 VirtReg, Order, CostPerUseLimit, FixedRegisters);
872 const AllocationOrder &Order) {
1064 AllocationOrder &Order,
1086 unsigned BestCand = calculateRegionSplitCost(VirtReg, Order, BestCost,
1098 AllocationOrder &Order,
1158 Cost += calcGlobalSplitCost(Cand, Order);
1175 AllocationOrder &Order,
1180 for (MCPhysReg PhysReg : Order) {
1185 calculateRegionSplitCostAroundReg(PhysReg, Order, BestCost, NumCands,
1237 AllocationOrder &Order) {
1281 calculateRegionSplitCostAroundReg(Hint, Order, Cost, NumCands, BestCand);
1297 AllocationOrder &Order,
1418 AllocationOrder &Order,
1571 AllocationOrder &Order,
1660 for (MCPhysReg PhysReg : Order) {
1801 unsigned RAGreedy::trySplit(const LiveInterval &VirtReg, AllocationOrder &Order,
1813 Register PhysReg = tryLocalSplit(VirtReg, Order, NewVRegs);
1816 return tryInstructionSplit(VirtReg, Order, NewVRegs);
1828 MCRegister PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs);
1834 return tryBlockSplit(VirtReg, Order, NewVRegs);
1945 /// \p Order defines the preferred allocation order for \p VirtReg.
1958 AllocationOrder &Order,
1992 for (MCRegister PhysReg : Order) {
2189 const LiveInterval &VirtReg, AllocationOrder &Order, MCRegister PhysReg,
2209 unsigned BestCand = calculateRegionSplitCost(VirtReg, Order, BestCost,
2429 auto Order =
2432 tryAssign(VirtReg, Order, NewVRegs, FixedRegisters)) {
2438 MCRegister CSRReg = tryAssignCSRFirstTime(VirtReg, Order, PhysReg,
2460 tryEvict(VirtReg, Order, NewVRegs, CostPerUseLimit,
2488 Register PhysReg = trySplit(VirtReg, Order, NewVRegs, FixedRegisters);
2496 return tryLastChanceRecoloring(VirtReg, Order, NewVRegs, FixedRegisters,