| /llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVISelLowering.cpp | 107 : OpReg; in getTypeReg() argument
116 doInsertBitcast(const SPIRVSubtarget & STI,MachineRegisterInfo * MRI,SPIRVGlobalRegistry & GR,MachineInstr & I,Register OpReg,unsigned OpIdx,SPIRVType * NewPtrType) doInsertBitcast() argument
156 Register OpReg = I.getOperand(OpIdx).getReg(); validatePtrTypes() local
190 Register OpReg = I.getOperand(OpIdx).getReg(); validateGroupWaitEventsPtr() local
211 Register OpReg = I.getOperand(OpIdx).getReg(); validateGroupAsyncCopyPtr() local
[all...] |
| H A D | SPIRVInstructionSelector.cpp | 713 Register OpReg = I.getOperand(1).getReg(); selectBitcast() local
1371 Register OpReg = I.getOperand(1).getReg(); selectFreeze() local
1432 Register OpReg = ResType->getOperand(2).getReg(); getArrayComponentCount() local
1488 isConstReg(MachineRegisterInfo * MRI,Register OpReg) isConstReg() argument
1511 Register OpReg = I.getOperand(OpIdx).getReg(); selectSplatVector() local
1915 Register OpReg = I.getOperand(i).getReg(); wrapIntoSpecConstantOp() local
2004 for (Register OpReg : CompositeArgs) selectIntrinsic() local
[all...] |
| /llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineConvergenceVerifier.cpp | 58 Register OpReg = MO.getReg(); findAndCheckConvergenceTokenUsed() local
|
| H A D | MachineInstr.cpp | 2070 Register OpReg = MO.getReg(); clearRegisterKills() local
|
| /llvm-project/llvm/lib/Target/AMDGPU/MCA/ |
| H A D | AMDGPUCustomBehaviour.cpp | 192 const MCAOperand *OpReg = Inst.getOperand(0); computeWaitCnt() local
|
| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 1731 Register OpReg = getRegForValue(TI->getOperand(0)); X86SelectBranch() local
1766 Register OpReg = getRegForValue(BI->getCondition()); X86SelectBranch() local
1788 unsigned CReg = 0, OpReg = 0; X86SelectShift() local
2360 Register OpReg = getRegForValue(Opnd); X86SelectSelect() local
2405 Register OpReg = getRegForValue(I->getOperand(0)); X86SelectIntToFP() local
2459 Register OpReg = getRegForValue(I->getOperand(0)); X86SelectFPExtOrFPTrunc() local
[all...] |
| H A D | X86SpeculativeLoadHardening.cpp | 1652 Register OpReg = Op->getReg(); hardenLoadAddr() local
|
| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | A15SDOptimizer.cpp | 297 Register OpReg = MO.getReg(); optimizeSDPattern() local
|
| H A D | ARMInstructionSelector.cpp | 1054 Register OpReg = I.getOperand(2).getReg(); in select() local
|
| H A D | ARMFastISel.cpp | 1263 Register OpReg = getRegForValue(TI->getOperand(0)); SelectBranch() local
|
| /llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86InstComments.cpp | 241 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); getRegOperandNumElts() local
|
| /llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 4611 unsigned OpReg = Inst.getOperand(2).getReg(); expandSge() local
4748 unsigned OpReg = Inst.getOperand(2).getReg(); expandSle() local
5439 unsigned OpReg = Inst.getOperand(2).getReg(); expandSeq() local
5520 unsigned OpReg = Inst.getOperand(2).getReg(); expandSne() local
[all...] |
| /llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FastISel.cpp | 1721 Register OpReg = getRegForValue(In); selectFNeg() local
|
| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 879 Register OpReg = Op.getReg(); in executeInWaterfallLoop() local
3599 Register OpReg = MI.getOperand(I).getReg(); getImageMapping() local
[all...] |
| H A D | AMDGPUInstructionSelector.cpp | 2652 Register OpReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); selectG_FNEG() local
2690 Register OpReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); selectG_FABS() local
|
| H A D | GCNHazardRecognizer.cpp | 2842 Register OpReg = Op.getReg(); fixVALUMaskWriteHazard() local
[all...] |
| H A D | SIInstrInfo.cpp | 6218 Register OpReg = Op.getReg(); legalizeGenericOperand() local
|
| /llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 5961 Register OpReg = MI.getOperand(0).getReg(); narrowScalarExtract() local
6027 Register OpReg = MI.getOperand(2).getReg(); narrowScalarInsert() local
8350 Register OpReg = MI.getOperand(1).getReg(); lowerAbsToAddXor() local
[all...] |
| /llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 5727 Register OpReg = I.getOperand(i).getReg(); selectBuildVector() local
7712 Register OpReg = MO.getReg(); fixupPHIOpBanks() local
|
| /llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 7467 unsigned OpReg = Inst.getOperand(i).getReg(); checkLowRegisterList() local
7481 unsigned OpReg = Inst.getOperand(i).getReg(); listContainsReg() local
|