Lines Matching defs:OpReg

1732         Register OpReg = getRegForValue(TI->getOperand(0));
1733         if (OpReg == 0) return false;
1736           .addReg(OpReg).addImm(1);
1767   Register OpReg = getRegForValue(BI->getCondition());
1768   if (OpReg == 0) return false;
1770   // In case OpReg is a K register, COPY to a GPR
1771   if (MRI.getRegClass(OpReg) == &X86::VK1RegClass) {
1772     unsigned KOpReg = OpReg;
1773     OpReg = createResultReg(&X86::GR32RegClass);
1775             TII.get(TargetOpcode::COPY), OpReg)
1777     OpReg = fastEmitInst_extractsubreg(MVT::i8, OpReg, X86::sub_8bit);
1780       .addReg(OpReg)
1789   unsigned CReg = 0, OpReg = 0;
1795     case Instruction::LShr: OpReg = X86::SHR8rCL; break;
1796     case Instruction::AShr: OpReg = X86::SAR8rCL; break;
1797     case Instruction::Shl:  OpReg = X86::SHL8rCL; break;
1805     case Instruction::LShr: OpReg = X86::SHR16rCL; break;
1806     case Instruction::AShr: OpReg = X86::SAR16rCL; break;
1807     case Instruction::Shl:  OpReg = X86::SHL16rCL; break;
1814     case Instruction::LShr: OpReg = X86::SHR32rCL; break;
1815     case Instruction::AShr: OpReg = X86::SAR32rCL; break;
1816     case Instruction::Shl:  OpReg = X86::SHL32rCL; break;
1823     case Instruction::LShr: OpReg = X86::SHR64rCL; break;
1824     case Instruction::AShr: OpReg = X86::SAR64rCL; break;
1825     case Instruction::Shl:  OpReg = X86::SHL64rCL; break;
1851   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(OpReg), ResultReg)
2114     // In case OpReg is a K register, COPY to a GPR
2315     // In case OpReg is a K register, COPY to a GPR
2361       Register OpReg = getRegForValue(Opnd);
2362       if (OpReg == 0)
2368         .addReg(OpReg);
2406   Register OpReg = getRegForValue(I->getOperand(0));
2407   if (OpReg == 0)
2438   Register ResultReg = fastEmitInst_rr(Opcode, RC, ImplicitDefReg, OpReg);
2460   Register OpReg = getRegForValue(I->getOperand(0));
2461   if (OpReg == 0)
2480   MIB.addReg(OpReg);