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Searched defs:Offset1 (Results 1 – 25 of 32) sorted by relevance

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/llvm-project/llvm/unittests/DebugInfo/DWARF/
H A DDWARFListTableTest.cpp97 std::optional<uint64_t> Offset1 = Header.getOffsetEntry(Extractor, 1); in TEST() local
/llvm-project/llvm/unittests/CodeGen/
H A DSelectionDAGAddressAnalysisTest.cpp158 TypeSize Offset1 = SubVecVT.getStoreSize(); TEST_F() local
188 TypeSize Offset1 = SubVecVT.getStoreSize(); TEST_F() local
279 TypeSize Offset1 = SubFixedVecVT2xi8.getStoreSize(); TEST_F() local
320 TypeSize Offset1 = SubFixedVecVT2xi8.getStoreSize(); TEST_F() local
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/llvm-project/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp205 int64_t Offset1 = 0; getHazardType() local
H A DARMBaseInstrInfo.cpp1949 areLoadsFromSameBasePtr(SDNode * Load1,SDNode * Load2,int64_t & Offset1,int64_t & Offset2) const areLoadsFromSameBasePtr() argument
2016 shouldScheduleLoadsNear(SDNode * Load1,SDNode * Load2,int64_t Offset1,int64_t Offset2,unsigned NumLoads) const shouldScheduleLoadsNear() argument
/llvm-project/llvm/lib/Transforms/AggressiveInstCombine/
H A DAggressiveInstCombine.cpp671 APInt Offset1(DL.getIndexTypeSizeInBits(Load1Ptr->getType()), 0); foldLoadsRecursive() local
806 APInt Offset1(DL.getIndexTypeSizeInBits(Load1Ptr->getType()), 0); foldConsecutiveLoads() local
/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h1445 areLoadsFromSameBasePtr(SDNode * Load1,SDNode * Load2,int64_t & Offset1,int64_t & Offset2) areLoadsFromSameBasePtr() argument
1459 shouldScheduleLoadsNear(SDNode * Load1,SDNode * Load2,int64_t Offset1,int64_t Offset2,unsigned NumLoads) shouldScheduleLoadsNear() argument
1562 shouldClusterMemOps(ArrayRef<const MachineOperand * > BaseOps1,int64_t Offset1,bool OffsetIsScalable1,ArrayRef<const MachineOperand * > BaseOps2,int64_t Offset2,bool OffsetIsScalable2,unsigned ClusterSize,unsigned NumBytes) shouldClusterMemOps() argument
/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp407 int64_t Offset1; apply() local
H A DHexagonISelLoweringHVX.cpp2224 SDValue Offset1 = DAG.getTargetConstant(HwLen, dl, MVT::i32); LowerHvxMaskedOp() local
/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsSizeReduction.cpp400 int64_t Offset1, Offset2; in ConsecutiveInstr() local
/llvm-project/llvm/lib/Transforms/Scalar/
H A DSeparateConstOffsetFromGEP.cpp1368 Value *Offset1 = First->getOperand(1); in swapGEPOperand() local
H A DConstraintElimination.cpp666 int64_t Offset1 = ADec.Offset; getConstraint() local
/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGSDNodes.cpp247 int64_t Offset1, Offset2; in ClusterNeighboringLoads() local
/llvm-project/llvm/lib/IR/
H A DValue.cpp1032 APInt Offset1(DL.getIndexTypeSizeInBits(Ptr1->getType()), 0); in getPointerOffsetFrom() local
/llvm-project/clang/lib/StaticAnalyzer/Checkers/
H A DContainerModeling.cpp968 SymbolRef Offset1, in invalidateIteratorPositions()
/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp1154 isDSOffset2Legal(SDValue Base,unsigned Offset0,unsigned Offset1,unsigned Size) const isDSOffset2Legal() argument
1259 SelectDSReadWrite2(SDValue Addr,SDValue & Base,SDValue & Offset0,SDValue & Offset1,unsigned Size) const SelectDSReadWrite2() argument
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H A DSIInstrInfo.cpp398 unsigned Offset1 = Offset1Op->getImm() & 0xff; getMemOperandsWithOffsetWidth() local
551 shouldClusterMemOps(ArrayRef<const MachineOperand * > BaseOps1,int64_t Offset1,bool OffsetIsScalable1,ArrayRef<const MachineOperand * > BaseOps2,int64_t Offset2,bool OffsetIsScalable2,unsigned ClusterSize,unsigned NumBytes) const shouldClusterMemOps() argument
596 shouldScheduleLoadsNear(SDNode * Load0,SDNode * Load1,int64_t Offset0,int64_t Offset1,unsigned NumLoads) const shouldScheduleLoadsNear() argument
3702 int64_t Offset0, Offset1; checkInstOffsetsDoNotOverlap() local
[all...]
H A DSILoadStoreOptimizer.cpp2040 uint64_t Offset1 = Src1->getImm(); processBaseWithConstOffset() local
H A DAMDGPUInstructionSelector.cpp1601 unsigned Offset1 = WaveRelease | (WaveDone << 1) | (Instruction << 4); selectDSOrderedIntrinsic() local
4711 isDSOffset2Legal(Register Base,int64_t Offset0,int64_t Offset1,unsigned Size) const isDSOffset2Legal() argument
/llvm-project/llvm/lib/Analysis/
H A DConstantFolding.cpp1252 APInt Offset1(IndexWidth, 0); ConstantFoldCompareInstOperands() local
/llvm-project/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp8652 areLoadsFromSameBasePtr(SDNode * Load1,SDNode * Load2,int64_t & Offset1,int64_t & Offset2) const areLoadsFromSameBasePtr() argument
8778 shouldScheduleLoadsNear(SDNode * Load1,SDNode * Load2,int64_t Offset1,int64_t Offset2,unsigned NumLoads) const shouldScheduleLoadsNear() argument
/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp4276 shouldClusterFI(const MachineFrameInfo & MFI,int FI1,int64_t Offset1,unsigned Opcode1,int FI2,int64_t Offset2,unsigned Opcode2) shouldClusterFI() argument
4344 int64_t Offset1 = FirstLdSt.getOperand(2).getImm(); shouldClusterMemOps() local
[all...]
/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.cpp2679 shouldClusterMemOps(ArrayRef<const MachineOperand * > BaseOps1,int64_t Offset1,bool OffsetIsScalable1,ArrayRef<const MachineOperand * > BaseOps2,int64_t Offset2,bool OffsetIsScalable2,unsigned ClusterSize,unsigned NumBytes) const shouldClusterMemOps() argument
/llvm-project/llvm/lib/CodeGen/
H A DMachinePipeliner.cpp863 int64_t Offset1, Offset2; addLoopCarriedDependences() local
/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp2930 int64_t Offset1 = 0, Offset2 = 0; shouldClusterMemOps() local
/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineAndOrXor.cpp1234 const APInt *Offset1 = nullptr, *Offset2 = nullptr; foldAndOrOfICmpsUsingRanges() local

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