| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 1463 SelectTable(SDNode * N,unsigned NumVecs,unsigned Opc,bool isExt) SelectTable() argument
1585 SelectLoad(SDNode * N,unsigned NumVecs,unsigned Opc,unsigned SubRegIdx) SelectLoad() argument
1614 SelectPostLoad(SDNode * N,unsigned NumVecs,unsigned Opc,unsigned SubRegIdx) SelectPostLoad() argument
1768 SelectCVTIntrinsic(SDNode * N,unsigned NumVecs,unsigned Opcode) SelectCVTIntrinsic() argument
1784 SelectDestructiveMultiIntrinsic(SDNode * N,unsigned NumVecs,bool IsZmMulti,unsigned Opcode,bool HasPred) SelectDestructiveMultiIntrinsic() argument
1822 SelectPredicatedLoad(SDNode * N,unsigned NumVecs,unsigned Scale,unsigned Opc_ri,unsigned Opc_rr,bool IsIntr) SelectPredicatedLoad() argument
1856 SelectContiguousMultiVectorLoad(SDNode * N,unsigned NumVecs,unsigned Scale,unsigned Opc_ri,unsigned Opc_rr) SelectContiguousMultiVectorLoad() argument
1890 SelectFrintFromVT(SDNode * N,unsigned NumVecs,unsigned Opcode) SelectFrintFromVT() argument
1925 SelectClamp(SDNode * N,unsigned NumVecs,unsigned Op) SelectClamp() argument
1974 SelectMultiVectorMove(SDNode * N,unsigned NumVecs,unsigned BaseReg,unsigned Op) SelectMultiVectorMove() argument
2008 SelectMultiVectorMoveZ(SDNode * N,unsigned NumVecs,unsigned Op,unsigned MaxIdx,unsigned Scale,unsigned BaseReg) SelectMultiVectorMoveZ() argument
2075 SelectStore(SDNode * N,unsigned NumVecs,unsigned Opc) SelectStore() argument
2095 SelectPredicatedStore(SDNode * N,unsigned NumVecs,unsigned Scale,unsigned Opc_rr,unsigned Opc_ri) SelectPredicatedStore() argument
2137 SelectPostStore(SDNode * N,unsigned NumVecs,unsigned Opc) SelectPostStore() argument
2193 SelectLoadLane(SDNode * N,unsigned NumVecs,unsigned Opc) SelectLoadLane() argument
2231 SelectPostLoadLane(SDNode * N,unsigned NumVecs,unsigned Opc) SelectPostLoadLane() argument
2285 SelectStoreLane(SDNode * N,unsigned NumVecs,unsigned Opc) SelectStoreLane() argument
2313 SelectPostStoreLane(SDNode * N,unsigned NumVecs,unsigned Opc) SelectPostStoreLane() argument
[all...] |
| H A D | AArch64TargetTransformInfo.cpp | 4027 unsigned NumVecs = (TpNumElts + LTNumElts - 1) / LTNumElts; getShuffleCost() local
|
| H A D | AArch64ISelLowering.cpp | 23004 unsigned NumVecs = 0; performNEONPostLDSTCombine() local
[all...] |
| /llvm-project/llvm/lib/Analysis/ |
| H A D | VectorUtils.cpp | 893 createInterleaveMask(unsigned VF,unsigned NumVecs) createInterleaveMask() argument
968 unsigned NumVecs = Vecs.size(); concatenateVectors() local
[all...] |
| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1945 GetVLDSTAlign(SDValue Align,const SDLoc & dl,unsigned NumVecs,bool is64BitVector) GetVLDSTAlign() argument
2110 isPerfectIncrement(SDValue Inc,EVT VecTy,unsigned NumVecs) isPerfectIncrement() argument
2115 SelectVLD(SDNode * N,bool isUpdating,unsigned NumVecs,const uint16_t * DOpcodes,const uint16_t * QOpcodes0,const uint16_t * QOpcodes1) SelectVLD() argument
2257 SelectVST(SDNode * N,bool isUpdating,unsigned NumVecs,const uint16_t * DOpcodes,const uint16_t * QOpcodes0,const uint16_t * QOpcodes1) SelectVST() argument
2412 SelectVLDSTLane(SDNode * N,bool IsLoad,bool isUpdating,unsigned NumVecs,const uint16_t * DOpcodes,const uint16_t * QOpcodes) SelectVLDSTLane() argument
2791 SelectMVE_VLD(SDNode * N,unsigned NumVecs,const uint16_t * const * Opcodes,bool HasWriteback) SelectMVE_VLD() argument
2954 SelectVLDDup(SDNode * N,bool IsIntrinsic,bool isUpdating,unsigned NumVecs,const uint16_t * DOpcodes,const uint16_t * QOpcodes0,const uint16_t * QOpcodes1) SelectVLDDup() argument
[all...] |
| H A D | ARMISelLowering.cpp | 15818 unsigned NumVecs = 0; TryCombineBaseUpdate() local
16310 unsigned NumVecs = 0; PerformMVEVLDCombine() local
16403 unsigned NumVecs = 0; CombineVLDDUP() local
[all...] |
| /llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 5793 selectVectorLoadIntrinsic(unsigned Opc,unsigned NumVecs,MachineInstr & I) selectVectorLoadIntrinsic() argument
5822 selectVectorLoadLaneIntrinsic(unsigned Opc,unsigned NumVecs,MachineInstr & I) selectVectorLoadLaneIntrinsic() argument
5875 selectVectorStoreIntrinsic(MachineInstr & I,unsigned NumVecs,unsigned Opc) selectVectorStoreIntrinsic() argument
5893 selectVectorStoreLaneIntrinsic(MachineInstr & I,unsigned NumVecs,unsigned Opc) selectVectorStoreLaneIntrinsic() argument
[all...] |
| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 10978 int NumVecs = 2; LowerINTRINSIC_WO_CHAIN() local
11561 unsigned NumVecs = VT.getSizeInBits() / 128; LowerVectorLoad() local
11607 unsigned NumVecs = 2; LowerVectorStore() local
[all...] |
| /llvm-project/clang/lib/CodeGen/ |
| H A D | CGBuiltin.cpp | 17779 unsigned NumVecs = 2; EmitPPCBuiltinExpr() local
|