Lines Matching defs:NumVecs
202 /// SelectVLD - Select NEON load intrinsics. NumVecs should be
205 /// For NumVecs <= 2, QOpcodes1 is not used.
206 void SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
210 /// SelectVST - Select NEON store intrinsics. NumVecs should
213 /// For NumVecs <= 2, QOpcodes1 is not used.
214 void SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
218 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
222 unsigned NumVecs, const uint16_t *DOpcodes,
274 /// SelectMVE_VLD - Select MVE interleaving load intrinsics. NumVecs
277 /// pointer points to a set of NumVecs sub-opcodes used for the
279 void SelectMVE_VLD(SDNode *N, unsigned NumVecs,
296 /// SelectVLDDup - Select NEON load-duplicate intrinsics. NumVecs
300 unsigned NumVecs, const uint16_t *DOpcodes,
339 SDValue GetVLDSTAlign(SDValue Align, const SDLoc &dl, unsigned NumVecs,
1936 unsigned NumVecs, bool is64BitVector) {
1937 unsigned NumRegs = NumVecs;
1938 if (!is64BitVector && NumVecs < 3)
2101 static bool isPerfectIncrement(SDValue Inc, EVT VecTy, unsigned NumVecs) {
2103 return C && C->getZExtValue() == VecTy.getSizeInBits() / 8 * NumVecs;
2106 void ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
2111 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
2124 Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector);
2149 if (NumVecs == 1)
2152 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
2169 if (is64BitVector || NumVecs <= 2) {
2176 bool IsImmUpdate = isPerfectIncrement(Inc, VT, NumVecs);
2228 if (NumVecs == 1) {
2239 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
2242 ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
2244 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2));
2248 void ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
2253 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");
2269 Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector);
2303 if (is64BitVector || NumVecs <= 2) {
2305 if (NumVecs == 1) {
2311 if (NumVecs == 2)
2317 SDValue V3 = (NumVecs == 3)
2335 bool IsImmUpdate = isPerfectIncrement(Inc, VT, NumVecs);
2368 SDValue V3 = (NumVecs == 3)
2403 unsigned NumVecs,
2407 assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
2421 unsigned Lane = N->getConstantOperandVal(Vec0Idx + NumVecs);
2426 if (NumVecs != 3) {
2428 unsigned NumBytes = NumVecs * VT.getScalarSizeInBits() / 8;
2460 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
2479 isPerfectIncrement(Inc, VT.getVectorElementType(), NumVecs);
2486 if (NumVecs == 2) {
2493 SDValue V3 = (NumVecs == 3)
2522 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
2525 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, 1));
2527 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2));
2782 void ARMDAGToDAGISel::SelectMVE_VLD(SDNode *N, unsigned NumVecs,
2803 EVT DataTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, NumVecs * 2);
2811 for (unsigned Stage = 0; Stage < NumVecs - 1; ++Stage) {
2824 CurDAG->getMachineNode(OurOpcodes[NumVecs - 1], Loc, ResultTys, Ops);
2828 for (i = 0; i < NumVecs; i++)
2945 bool isUpdating, unsigned NumVecs,
2950 assert(NumVecs >= 1 && NumVecs <= 4 && "VLDDup NumVecs out-of-range");
2963 if (NumVecs != 3) {
2965 unsigned NumBytes = NumVecs * VT.getScalarSizeInBits() / 8;
2997 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
3015 : (NumVecs == 1) ? QOpcodes0[OpcodeIndex]
3020 isPerfectIncrement(Inc, VT.getVectorElementType(), NumVecs);
3030 if (is64BitVector || NumVecs == 1) {
3053 if (NumVecs == 1) {
3059 for (unsigned Vec = 0; Vec != NumVecs; ++Vec) {
3064 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdDup, 1));
3066 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2));