/llvm-project/clang/include/clang/Analysis/Analyses/ |
H A D | ThreadSafetyLogical.h | 27 Not enumerator 86 Not(LExpr *Exp) : LExpr(LExpr::Not), Exp(Exp) {} in Not() function
|
/llvm-project/clang/include/clang/Analysis/FlowSensitive/ |
H A D | Formula.h | 58 Not, /// True if its only operand is false enumerator
|
/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyFastISel.cpp | 428 getRegForI1Value(const Value * V,const BasicBlock * BB,bool & Not) getRegForI1Value() argument 915 bool Not; selectSelect() local 1107 bool Not = false; selectFCmp() local 1320 bool Not; selectBr() local [all...] |
/llvm-project/mlir/lib/TableGen/ |
H A D | Predicate.cpp | 94 Not, global() enumerator
|
/llvm-project/llvm/utils/TableGen/ |
H A D | CompressInstEmitter.cpp | 692 StringRef Not = Op.first ? "!" : ""; emitCompressInstEmitter() local 703 StringRef Not = Op.first ? "!" : ""; emitCompressInstEmitter() local
|
/llvm-project/llvm/unittests/CodeGen/ |
H A D | SelectionDAGPatternMatchTest.cpp | 193 SDValue Not = DAG->getNOT(DL, Op0, Int32VT); TEST_F() local
|
/llvm-project/llvm/unittests/IR/ |
H A D | PatternMatch.cpp | 778 TEST_F(PatternMatchTest,Not) TEST_F() argument 782 Instruction *Not = BinaryOperator::CreateXor(C1, C2); TEST_F() local 2198 Value *Not = IRB.CreateXor(VectorZero, VectorOnes); TEST_F() local
|
/llvm-project/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineAddSub.cpp | 1663 Value *Not = Builder.CreateXor(A, AllOnes); visitAdd() local 2527 Value *Not = Builder.CreateNot(Op1); visitSub() local 2533 Value *Not = Builder.CreateNot(Op0); visitSub() local
|
H A D | InstCombineCompares.cpp | 4182 isMaskOrZero(const Value * V,bool Not,const SimplifyQuery & Q,unsigned Depth=0) isMaskOrZero() argument [all...] |
/llvm-project/flang/lib/Evaluate/ |
H A D | formatting.cpp | 281 Not, // which binds *less* tightly in Fortran than relations global() enumerator
|
/llvm-project/llvm/include/llvm/MC/ |
H A D | MCExpr.h | 437 Not, ///< Bitwise negation. global() enumerator
|
/llvm-project/llvm/lib/Target/X86/ |
H A D | X86InstCombineIntrinsic.cpp | 695 auto Xnor = [&](auto Lhs, auto Rhs) { return Not(Xor(Lhs, Rhs)); }; in simplifyTernarylogic() local [all...] |
H A D | X86ISelLowering.cpp | 5125 if (SDValue Not = IsNOT(V.getOperand(0), DAG)) { IsNOT() local 30557 bool Not = false; FindSingleBitChange() local 48861 if (SDValue Not = IsNOT(N0, DAG)) { combineAndNotIntoANDNP() local 48864 } else if (SDValue Not = IsNOT(N1, DAG)) { combineAndNotIntoANDNP() local 48909 if (SDValue Not = IsNOT(Src, DAG)) { combineAndShuffleNot() local 48925 if (SDValue Not = GetNot(N0)) { combineAndShuffleNot() local 48928 } else if (SDValue Not = GetNot(N1)) { combineAndShuffleNot() local 53351 if (SDValue Not = IsNOT(N0, DAG)) combineAndnp() local 53357 if (SDValue Not = IsNOT(N1, DAG)) combineAndnp() local 53384 SDValue Not = getConstVector(EltBits0, VT, DAG, DL); combineAndnp() local [all...] |
/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 2625 SDValue Not = lowerShiftLeftParts() local 2664 SDValue Not = lowerShiftRightParts() local
|
/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIInstrInfo.cpp | 7697 MachineInstr *Not = lowerScalarXnor() local 7729 MachineInstr &Not = *BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), NewDest) splitScalarNotBinop() local 7754 MachineInstr &Not = *BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), Interm) splitScalarBinOpN2() local
|
H A D | AMDGPUISelLowering.cpp | 2439 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64); LowerFTRUNC() local
|
H A D | AMDGPULegalizerInfo.cpp | 2542 auto Not = B.buildNot(S64, Shr); legalizeIntrinsicTrunc() local
|
/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | TargetLowering.cpp | 1632 SDValue Not = TLO.DAG.getNOT(dl, Op0.getOperand(0), VT); SimplifyDemandedBits() local 5272 SDValue Not = DAG.getNOT(dl, N1, OpVT); SimplifySetCC() local 9093 SDValue Not = DAG.getNode(ISD::VP_XOR, dl, VT, Op, expandVPCTTZ() local 10326 SDValue Not = DAG.getNOT(dl, OverflowMask, VT); expandAddSubSat() local [all...] |
H A D | DAGCombiner.cpp | 2608 SDValue Not = ShiftOp.getOperand(0); foldAddSubOfSignBit() local 2705 SDValue Not = DAG.getNOT(DL, X, X.getValueType()); visitADDLike() local 2861 SDValue Not = DAG.getNOT(DL, N0.getOperand(0), VT); visitADDLike() local 2869 SDValue Not = DAG.getNOT(DL, N0.getOperand(1), VT); visitADDLike() local 3173 SDValue Not = DAG.getNOT(DL, N0.getOperand(0), VT); visitADDLikeCommutative() local 11599 SDValue Not = DAG.getNOT(DL, Sra, VT); foldVSelectToSignBitSplatMask() local [all...] |
/llvm-project/llvm/lib/Transforms/Vectorize/ |
H A D | VPlan.h | 1189 Not, global() enumerator
|
/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelDAGToDAG.cpp | 2807 MachineSDNode *Not = selectShiftMask() local
|
/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | CombinerHelper.cpp | 3539 auto Not = Builder.buildNot(MRI.getType(X), X); applyXorOfAndWithSameReg() local 6743 Register Not = MRI.createGenericVirtualRegister(CondTy); tryFoldSelectOfConstants() local [all...] |
H A D | LegalizerHelper.cpp | 7842 Register Not = IsAdd ? MIRBuilder.buildNot(Ty, LHS).getReg(0) : LHS; lowerAddSubSatToMinMax() local [all...] |
/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelDAGToDAG.cpp | 3724 MachineSDNode *Not = tryShiftAmountMod() local
|
/llvm-project/compiler-rt/lib/msan/tests/ |
H A D | msan_test.cpp | 425 TEST(MemorySanitizer, Not) { in TEST() argument
|