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Searched defs:NewOpc (Results 1 – 25 of 71) sorted by relevance

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/llvm-project/llvm/lib/Target/X86/
H A DX86FixupInstTuning.cpp133 if (!NewOpcPreferable(NewOpc)) in processInstruction() argument
148 if (!NewOpcPreferable(NewOpc)) in processInstruction() argument
107 __anon1e043a930502(unsigned NewOpc, bool ReplaceInTie = true) processInstruction() argument
162 __anon1e043a930802(unsigned NewOpc) processInstruction() argument
186 __anon1e043a930902(unsigned NewOpc, unsigned MaskImm) processInstruction() argument
195 __anon1e043a930a02(unsigned NewOpc) processInstruction() argument
207 __anon1e043a930b02(unsigned NewOpcIntDomain, unsigned NewOpc) processInstruction() argument
213 __anon1e043a930c02(unsigned NewOpcIntDomain, unsigned NewOpc) processInstruction() argument
223 __anon1e043a930e02(unsigned NewOpc) processInstruction() argument
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H A DX86CompressEVEX.cpp117 (void)NewOpc; in performCustomAdjustments() argument
243 unsigned NewOpc = IsRedundantNDD CompressEVEXImpl() local
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H A DX86FixupLEAs.cpp810 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode()); in processInstrForSlow3OpLEA() local
848 unsigned NewOpc = in processInstrForSlow3OpLEA() local
854 unsigned NewOpc = getADDriFromLEA(MI.getOpcode(), Offset); in processInstrForSlow3OpLEA() local
882 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode()); in processInstrForSlow3OpLEA() local
905 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode()); in processInstrForSlow3OpLEA() local
H A DX86ISelDAGToDAG.cpp1166 unsigned NewOpc; in PreprocessISelDAG() local
1133 unsigned NewOpc; PreprocessISelDAG() local
1188 unsigned NewOpc; PreprocessISelDAG() local
1605 unsigned NewOpc; PostprocessISelDAG() local
1667 unsigned NewOpc; PostprocessISelDAG() local
3629 unsigned NewOpc = SelectOpcode(X86::NEG64m, X86::NEG32m, X86::NEG16m, foldLoadStoreIntoMemOperand() local
3644 unsigned NewOpc = foldLoadStoreIntoMemOperand() local
3714 unsigned NewOpc = SelectRegOpcode(Opc); foldLoadStoreIntoMemOperand() local
4164 unsigned NewOpc = NVT == MVT::i64 ? X86::MOV32ri64 : X86::MOV32ri; matchBEXTRFromAndImm() local
4182 unsigned NewOpc = NVT == MVT::i64 ? X86::MOV32ri64 : X86::MOV32ri; matchBEXTRFromAndImm() local
4206 unsigned NewOpc = NVT == MVT::i64 ? GET_ND_IF_ENABLED(X86::SHR64ri) matchBEXTRFromAndImm() local
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/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86EncodingOptimization.cpp25 unsigned NewOpc = 0; in optimizeInstFromVEX3ToVEX2() local
105 unsigned NewOpc; in optimizeShiftRotateWithImmediateOne() local
277 unsigned NewOpc; optimizeVPCMPWithImmediateOneOrSix() local
290 unsigned NewOpc; optimizeMOVSX() local
314 unsigned NewOpc; optimizeINCDEC() local
342 unsigned NewOpc; optimizeMOV() local
397 unsigned NewOpc; optimizeToFixedRegisterForm() local
474 unsigned NewOpc; optimizeToShortImmediateForm() local
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/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenMemAbsolute.cpp113 if (!IsLoad && !isValidIndexedStore(NextOpc, NewOpc)) in runOnMachineFunction() local
217 isValidIndexedLoad(int & Opc,int & NewOpc) isValidIndexedLoad() argument
246 isValidIndexedStore(int & Opc,int & NewOpc) isValidIndexedStore() argument
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H A DHexagonRDFOpt.cpp229 unsigned OpNum, NewOpc; in rewrite() local
H A DHexagonGenPredicate.cpp387 unsigned NewOpc = getPredForm(Opc); in convertToPredForm() local
/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CondBrTuning.cpp98 unsigned NewOpc = TII->convertToFlagSettingOpc(MI.getOpcode()); in convertToFlagSetting() local
H A DAArch64AdvSIMDScalarPass.cpp292 unsigned NewOpc = getTransformOpcode(OldOpc); in transformInstruction() local
/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVFoldMasks.cpp
H A DRISCVExpandPseudoInsts.cpp205 unsigned NewOpc; expandCCOp() local
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/llvm-project/llvm/lib/Target/ARM/
H A DARMExpandPseudoInsts.cpp876 unsigned NewOpc = in ExpandMQQPRLoadStore() local
2144 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBITd : ARM::VBITq; ExpandMI() local
2154 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBIFd : ARM::VBIFq; ExpandMI() local
2164 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBSLd : ARM::VBSLq; ExpandMI() local
2440 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16; ExpandMI() local
2482 unsigned NewOpc; ExpandMI() local
2776 unsigned NewOpc = ARM::VLDMDIA; ExpandMI() local
2807 unsigned NewOpc = ARM::VSTMDIA; ExpandMI() local
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H A DARMLoadStoreOptimizer.cpp1501 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::add); in MergeBaseUpdateLoadStore() local
1349 unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode); MergeBaseUpdateLSMultiple() local
1638 unsigned NewOpc; MergeBaseUpdateLSDouble() local
1735 InsertLDR_STR(MachineBasicBlock & MBB,MachineBasicBlock::iterator & MBBI,int Offset,bool isDef,unsigned NewOpc,unsigned Reg,bool RegDeadKill,bool RegUndef,unsigned BaseReg,bool BaseKill,bool BaseUndef,ARMCC::CondCodes Pred,unsigned PredReg,const TargetInstrInfo * TII,MachineInstr * MI) InsertLDR_STR() argument
1807 unsigned NewOpc = (isLd) FixInvalidRegPairOp() local
1831 unsigned NewOpc = (isLd) FixInvalidRegPairOp() local
2059 unsigned NewOpc = (isThumb2 ? ARM::t2LDMIA_RET : ARM::LDMIA_RET); MergeReturnIntoLDM() local
2256 CanFormLdStDWord(MachineInstr * Op0,MachineInstr * Op1,DebugLoc & dl,unsigned & NewOpc,Register & FirstReg,Register & SecondReg,Register & BaseReg,int & Offset,Register & PredReg,ARMCC::CondCodes & Pred,bool & isT2) CanFormLdStDWord() argument
2420 unsigned NewOpc = 0; RescheduleOps() local
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H A DThumb2InstrInfo.cpp610 unsigned NewOpc = isSub ? IsSP ? ARM::t2SUBspImm12 : ARM::t2SUBri12 rewriteT2FrameIndex() local
643 unsigned NewOpc = Opcode; rewriteT2FrameIndex() local
H A DARMConstantIslandPass.cpp1845 unsigned NewOpc = 0; optimizeThumb2Instructions() local
1896 unsigned NewOpc = 0; optimizeThumb2Branches() local
1930 unsigned NewOpc = 0; optimizeThumb2Branches() member
1944 unsigned NewOpc = 0; optimizeThumb2Branches() local
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H A DARMInstructionSelector.cpp910 unsigned NewOpc = selectSimpleExtOpc(I.getOpcode(), SrcSize); in select() local
1106 const auto NewOpc = selectLoadStoreOpCode(I.getOpcode(), RegBank, ValSize); select() local
/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostSelectOptimize.cpp270 unsigned NewOpc = getNonFlagSettingVariant(II.getOpcode()); in optimizeNZCVDefs() local
/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiMemAluCombiner.cpp251 unsigned NewOpc = mergedOpcode(MemInstr->getOpcode(), AluOffset.isImm()); in insertMergedInstruction() local
/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp575 unsigned NewOpc = getLoadStoreOp(Ty, RB, Opc, MemOp.getAlign()); selectLoadStoreOp() local
638 unsigned NewOpc = getLeaOP(Ty, STI); selectFrameIndexOrGep() local
689 unsigned NewOpc = getLeaOP(Ty, STI); selectGlobalValue() local
721 unsigned NewOpc; selectConstant() local
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/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFoldOperands.cpp477 const unsigned NewOpc = TryAK ? AMDGPU::S_FMAAK_F32 : AMDGPU::S_FMAMK_F32; tryAddToFoldList() local
514 unsigned NewOpc = macToMad(Opc); tryAddToFoldList() local
826 unsigned NewOpc = AMDGPU::getFlatScratchInstSSfromSV(Opc); foldOperand() local
H A DAMDGPUPostLegalizerCombiner.cpp347 unsigned NewOpc = AMDGPU::G_AMDGPU_CVT_F32_UBYTE0 + MatchInfo.ShiftOffset / 8; in applyCvtF32UByteN() local
/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstrInfo.cpp685 genInstrWithNewOpc(unsigned NewOpc,MachineBasicBlock::iterator I) const genInstrWithNewOpc() argument
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H A DMipsBranchExpansion.cpp341 unsigned NewOpc = TII->getOppositeBranchOpc(Br->getOpcode()); replaceBranch() local
/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCInstructionSelector.cpp740 const unsigned NewOpc = selectLoadStoreOp( in select() local

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