Lines Matching defs:NewOpc

1347   unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode);
1348   MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc))
1499   unsigned NewOpc;
1501     NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::add);
1503     NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::sub);
1509     NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::add);
1511         (!isAM5 && !isLegalAddressImm(NewOpc, Offset, TII))) {
1512       NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::sub);
1513       if (isAM5 || !isLegalAddressImm(NewOpc, Offset, TII))
1529     auto MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc))
1542       if (NewOpc == ARM::LDR_PRE_IMM || NewOpc == ARM::LDRB_PRE_IMM) {
1544             BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg())
1556             BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg())
1569           BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg())
1583     if (isAM2 && NewOpc == ARM::STR_POST_IMM) {
1586       auto MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc), Base)
1597       auto MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc), Base)
1636   unsigned NewOpc;
1638     NewOpc = Opcode == ARM::t2LDRDi8 ? ARM::t2LDRD_PRE : ARM::t2STRD_PRE;
1643     NewOpc = Opcode == ARM::t2LDRDi8 ? ARM::t2LDRD_POST : ARM::t2STRD_POST;
1644     if (!isLegalAddressImm(NewOpc, Offset, TII))
1651   MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc));
1652   if (NewOpc == ARM::t2LDRD_PRE || NewOpc == ARM::t2LDRD_POST) {
1655     assert(NewOpc == ARM::t2STRD_PRE || NewOpc == ARM::t2STRD_POST);
1661          TII->get(NewOpc).getNumOperands() == 7 &&
1733                           bool isDef, unsigned NewOpc, unsigned Reg,
1740                                       TII->get(NewOpc))
1749                                       TII->get(NewOpc))
1805     unsigned NewOpc = (isLd)
1809       BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc))
1817       BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc))
1829     unsigned NewOpc = (isLd)
1843       InsertLDR_STR(MBB, MBBI, OffImm, isLd, NewOpc, EvenReg, EvenDeadKill,
1857       InsertLDR_STR(MBB, MBBI, OffImm, isLd, NewOpc, EvenReg, EvenDeadKill,
2057       unsigned NewOpc = (isThumb2 ? ARM::t2LDMIA_RET : ARM::LDMIA_RET);
2060       PrevMI.setDesc(TII->get(NewOpc));
2169                           unsigned &NewOpc, Register &EvenReg, Register &OddReg,
2254     MachineInstr *Op0, MachineInstr *Op1, DebugLoc &dl, unsigned &NewOpc,
2265     NewOpc = ARM::LDRD;
2267     NewOpc = ARM::STRD;
2269     NewOpc = ARM::t2LDRDi8;
2273     NewOpc = ARM::t2STRDi8;
2418         unsigned NewOpc = 0;
2421         if (NumMove == 2 && CanFormLdStDWord(Op0, Op1, dl, NewOpc,
2427           const MCInstrDesc &MCID = TII->get(NewOpc);