| /freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | Utils.cpp | 44 constrainRegToClass(MachineRegisterInfo & MRI,const TargetInstrInfo & TII,const RegisterBankInfo & RBI,Register Reg,const TargetRegisterClass & RegClass) constrainRegToClass() argument
56 constrainOperandRegClass(const MachineFunction & MF,const TargetRegisterInfo & TRI,MachineRegisterInfo & MRI,const TargetInstrInfo & TII,const RegisterBankInfo & RBI,MachineInstr & InsertPt,const TargetRegisterClass & RegClass,MachineOperand & RegMO) constrainOperandRegClass() argument
108 constrainOperandRegClass(const MachineFunction & MF,const TargetRegisterInfo & TRI,MachineRegisterInfo & MRI,const TargetInstrInfo & TII,const RegisterBankInfo & RBI,MachineInstr & InsertPt,const MCInstrDesc & II,MachineOperand & RegMO,unsigned OpIdx) constrainOperandRegClass() argument
161 MachineRegisterInfo &MRI = MF.getRegInfo(); constrainSelectedInstRegOperands() local
200 canReplaceReg(Register DstReg,Register SrcReg,MachineRegisterInfo & MRI) canReplaceReg() argument
221 isTriviallyDead(const MachineInstr & MI,const MachineRegisterInfo & MRI) isTriviallyDead() argument
294 getIConstantVRegVal(Register VReg,const MachineRegisterInfo & MRI) getIConstantVRegVal() argument
305 getIConstantVRegSExtVal(Register VReg,const MachineRegisterInfo & MRI) getIConstantVRegSExtVal() argument
318 getConstantVRegValWithLookThrough(Register VReg,const MachineRegisterInfo & MRI,IsOpcodeFn IsConstantOpcode,GetAPCstFn getAPCstValue,bool LookThroughInstrs=true,bool LookThroughAnyExt=false) getConstantVRegValWithLookThrough() argument
415 getIConstantVRegValWithLookThrough(Register VReg,const MachineRegisterInfo & MRI,bool LookThroughInstrs) getIConstantVRegValWithLookThrough() argument
421 getAnyConstantVRegValWithLookThrough(Register VReg,const MachineRegisterInfo & MRI,bool LookThroughInstrs,bool LookThroughAnyExt) getAnyConstantVRegValWithLookThrough() argument
429 getFConstantVRegValWithLookThrough(Register VReg,const MachineRegisterInfo & MRI,bool LookThroughInstrs) getFConstantVRegValWithLookThrough() argument
439 getConstantFPVRegVal(Register VReg,const MachineRegisterInfo & MRI) getConstantFPVRegVal() argument
447 getDefSrcRegIgnoringCopies(Register Reg,const MachineRegisterInfo & MRI) getDefSrcRegIgnoringCopies() argument
467 getDefIgnoringCopies(Register Reg,const MachineRegisterInfo & MRI) getDefIgnoringCopies() argument
474 getSrcRegIgnoringCopies(Register Reg,const MachineRegisterInfo & MRI) getSrcRegIgnoringCopies() argument
483 extractParts(Register Reg,LLT Ty,int NumParts,SmallVectorImpl<Register> & VRegs,MachineIRBuilder & MIRBuilder,MachineRegisterInfo & MRI) extractParts() argument
493 extractParts(Register Reg,LLT RegTy,LLT MainTy,LLT & LeftoverTy,SmallVectorImpl<Register> & VRegs,SmallVectorImpl<Register> & LeftoverRegs,MachineIRBuilder & MIRBuilder,MachineRegisterInfo & MRI) extractParts() argument
587 extractVectorParts(Register Reg,unsigned NumElts,SmallVectorImpl<Register> & VRegs,MachineIRBuilder & MIRBuilder,MachineRegisterInfo & MRI) extractVectorParts() argument
627 getOpcodeDef(unsigned Opcode,Register Reg,const MachineRegisterInfo & MRI) getOpcodeDef() argument
648 ConstantFoldBinOp(unsigned Opcode,const Register Op1,const Register Op2,const MachineRegisterInfo & MRI) ConstantFoldBinOp() argument
712 ConstantFoldFPBinOp(unsigned Opcode,const Register Op1,const Register Op2,const MachineRegisterInfo & MRI) ConstantFoldFPBinOp() argument
767 ConstantFoldVectorBinop(unsigned Opcode,const Register Op1,const Register Op2,const MachineRegisterInfo & MRI) ConstantFoldVectorBinop() argument
787 isKnownNeverNaN(Register Val,const MachineRegisterInfo & MRI,bool SNaN) isKnownNeverNaN() argument
886 MachineRegisterInfo &MRI = MF.getRegInfo(); getFunctionLiveInPhysReg() local
915 ConstantFoldExtOp(unsigned Opcode,const Register Op1,uint64_t Imm,const MachineRegisterInfo & MRI) ConstantFoldExtOp() argument
932 ConstantFoldCastOp(unsigned Opcode,LLT DstTy,const Register Op0,const MachineRegisterInfo & MRI) ConstantFoldCastOp() argument
955 ConstantFoldIntToFloat(unsigned Opcode,LLT DstTy,Register Src,const MachineRegisterInfo & MRI) ConstantFoldIntToFloat() argument
967 ConstantFoldCTLZ(Register Src,const MachineRegisterInfo & MRI) ConstantFoldCTLZ() argument
997 isKnownToBeAPowerOfTwo(Register Reg,const MachineRegisterInfo & MRI,GISelKnownBits * KB) isKnownToBeAPowerOfTwo() argument
1206 getAnyConstantSplat(Register VReg,const MachineRegisterInfo & MRI,bool AllowUndef) getAnyConstantSplat() argument
1248 isBuildVectorConstantSplat(const Register Reg,const MachineRegisterInfo & MRI,int64_t SplatValue,bool AllowUndef) isBuildVectorConstantSplat() argument
1256 isBuildVectorConstantSplat(const MachineInstr & MI,const MachineRegisterInfo & MRI,int64_t SplatValue,bool AllowUndef) isBuildVectorConstantSplat() argument
1263 getIConstantSplatVal(const Register Reg,const MachineRegisterInfo & MRI) getIConstantSplatVal() argument
1276 getIConstantSplatVal(const MachineInstr & MI,const MachineRegisterInfo & MRI) getIConstantSplatVal() argument
1282 getIConstantSplatSExtVal(const Register Reg,const MachineRegisterInfo & MRI) getIConstantSplatSExtVal() argument
1291 getIConstantSplatSExtVal(const MachineInstr & MI,const MachineRegisterInfo & MRI) getIConstantSplatSExtVal() argument
1296 getFConstantSplat(Register VReg,const MachineRegisterInfo & MRI,bool AllowUndef) getFConstantSplat() argument
1304 isBuildVectorAllZeros(const MachineInstr & MI,const MachineRegisterInfo & MRI,bool AllowUndef) isBuildVectorAllZeros() argument
1310 isBuildVectorAllOnes(const MachineInstr & MI,const MachineRegisterInfo & MRI,bool AllowUndef) isBuildVectorAllOnes() argument
1316 getVectorSplat(const MachineInstr & MI,const MachineRegisterInfo & MRI) getVectorSplat() argument
1330 isConstantScalar(const MachineInstr & MI,const MachineRegisterInfo & MRI,bool AllowFP=true,bool AllowOpaqueConstants=true) isConstantScalar() argument
1350 isConstantOrConstantVector(MachineInstr & MI,const MachineRegisterInfo & MRI) isConstantOrConstantVector() argument
1367 isConstantOrConstantVector(const MachineInstr & MI,const MachineRegisterInfo & MRI,bool AllowFP,bool AllowOpaqueConstants) isConstantOrConstantVector() argument
1387 isConstantOrConstantSplatVector(MachineInstr & MI,const MachineRegisterInfo & MRI) isConstantOrConstantSplatVector() argument
1399 isNullOrNullSplat(const MachineInstr & MI,const MachineRegisterInfo & MRI,bool AllowUndefs) isNullOrNullSplat() argument
1417 isAllOnesOrAllOnesSplat(const MachineInstr & MI,const MachineRegisterInfo & MRI,bool AllowUndefs) isAllOnesOrAllOnesSplat() argument
1432 matchUnaryPredicate(const MachineRegisterInfo & MRI,Register Reg,std::function<bool (const Constant * ConstVal)> Match,bool AllowUndefs) matchUnaryPredicate() argument
1507 saveUsesAndErase(MachineInstr & MI,MachineRegisterInfo & MRI,LostDebugLocObserver * LocObserver,SmallInstListTy & DeadInstChain) saveUsesAndErase() argument
1522 eraseInstrs(ArrayRef<MachineInstr * > DeadInstrs,MachineRegisterInfo & MRI,LostDebugLocObserver * LocObserver) eraseInstrs() argument
1536 eraseInstr(MachineInstr & MI,MachineRegisterInfo & MRI,LostDebugLocObserver * LocObserver) eraseInstr() argument
1541 salvageDebugInfo(const MachineRegisterInfo & MRI,MachineInstr & MI) salvageDebugInfo() argument
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerLowering.cpp | 230 bool matchZip(MachineInstr &MI, MachineRegisterInfo &MRI, in matchREV() argument
259 matchTRN(MachineInstr & MI,MachineRegisterInfo & MRI,ShuffleVectorPseudo & MatchInfo) matchTRN() argument
280 matchUZP(MachineInstr & MI,MachineRegisterInfo & MRI,ShuffleVectorPseudo & MatchInfo) matchUZP() argument
296 matchZip(MachineInstr & MI,MachineRegisterInfo & MRI,ShuffleVectorPseudo & MatchInfo) matchZip() argument
314 matchDupFromInsertVectorElt(int Lane,MachineInstr & MI,MachineRegisterInfo & MRI,ShuffleVectorPseudo & MatchInfo) matchDupFromInsertVectorElt() argument
354 matchDupFromBuildVector(int Lane,MachineInstr & MI,MachineRegisterInfo & MRI,ShuffleVectorPseudo & MatchInfo) matchDupFromBuildVector() argument
369 matchDup(MachineInstr & MI,MachineRegisterInfo & MRI,ShuffleVectorPseudo & MatchInfo) matchDup() argument
415 matchEXT(MachineInstr & MI,MachineRegisterInfo & MRI,ShuffleVectorPseudo & MatchInfo) matchEXT() argument
482 matchINS(MachineInstr & MI,MachineRegisterInfo & MRI,std::tuple<Register,int,Register,int> & MatchInfo) matchINS() argument
509 applyINS(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & Builder,std::tuple<Register,int,Register,int> & MatchInfo) applyINS() argument
528 isVShiftRImm(Register Reg,MachineRegisterInfo & MRI,LLT Ty,int64_t & Cnt) isVShiftRImm() argument
541 matchVAshrLshrImm(MachineInstr & MI,MachineRegisterInfo & MRI,int64_t & Imm) matchVAshrLshrImm() argument
551 applyVAshrLshrImm(MachineInstr & MI,MachineRegisterInfo & MRI,int64_t & Imm) applyVAshrLshrImm() argument
572 tryAdjustICmpImmAndPred(Register RHS,CmpInst::Predicate P,const MachineRegisterInfo & MRI) tryAdjustICmpImmAndPred() argument
668 matchAdjustICmpImmAndPred(MachineInstr & MI,const MachineRegisterInfo & MRI,std::pair<uint64_t,CmpInst::Predicate> & MatchInfo) matchAdjustICmpImmAndPred() argument
685 MachineRegisterInfo &MRI = *MIB.getMRI(); applyAdjustICmpImmAndPred() local
694 matchDupLane(MachineInstr & MI,MachineRegisterInfo & MRI,std::pair<unsigned,int> & MatchInfo) matchDupLane() argument
750 applyDupLane(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & B,std::pair<unsigned,int> & MatchInfo) applyDupLane() argument
772 matchScalarizeVectorUnmerge(MachineInstr & MI,MachineRegisterInfo & MRI) matchScalarizeVectorUnmerge() argument
780 applyScalarizeVectorUnmerge(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & B) applyScalarizeVectorUnmerge() argument
793 matchBuildVectorToDup(MachineInstr & MI,MachineRegisterInfo & MRI) matchBuildVectorToDup() argument
807 applyBuildVectorToDup(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & B) applyBuildVectorToDup() argument
817 getCmpOperandFoldingProfit(Register CmpOp,MachineRegisterInfo & MRI) getCmpOperandFoldingProfit() argument
871 trySwapICmpOperands(MachineInstr & MI,MachineRegisterInfo & MRI) trySwapICmpOperands() argument
924 getVectorFCMP(AArch64CC::CondCode CC,Register LHS,Register RHS,bool IsZero,bool NoNans,MachineRegisterInfo & MRI) getVectorFCMP() argument
977 matchLowerVectorFCMP(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & MIB) matchLowerVectorFCMP() argument
997 applyLowerVectorFCMP(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & MIB) applyLowerVectorFCMP() argument
1050 matchFormTruncstore(MachineInstr & MI,MachineRegisterInfo & MRI,Register & SrcReg) matchFormTruncstore() argument
1063 applyFormTruncstore(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & B,GISelChangeObserver & Observer,Register & SrcReg) applyFormTruncstore() argument
1075 matchVectorSextInReg(MachineInstr & MI,MachineRegisterInfo & MRI) matchVectorSextInReg() argument
1082 applyVectorSextInReg(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & B,GISelChangeObserver & Observer) applyVectorSextInReg() argument
1092 matchUnmergeExtToUnmerge(MachineInstr & MI,MachineRegisterInfo & MRI,Register & MatchInfo) matchUnmergeExtToUnmerge() argument
1122 applyUnmergeExtToUnmerge(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & B,GISelChangeObserver & Observer,Register & SrcReg) applyUnmergeExtToUnmerge() argument
1139 matchExtMulToMULL(MachineInstr & MI,MachineRegisterInfo & MRI) matchExtMulToMULL() argument
1165 applyExtMulToMULL(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & B,GISelChangeObserver & Observer) applyExtMulToMULL() argument
[all...] |
| H A D | AArch64GlobalISelUtils.cpp | 22 const MachineRegisterInfo &MRI) { in getAArch64VectorSplat() argument
36 const MachineRegisterInfo &MRI) { in getAArch64VectorSplatScalar() argument
45 const MachineRegisterInfo &MRI) { in isCMN() argument
67 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); in tryEmitBZero() local
[all...] |
| H A D | AArch64PostLegalizerCombiner.cpp | 67 MachineInstr &MI, MachineRegisterInfo &MRI, in matchExtractVecEltPairwiseAdd() argument
110 MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilde in applyExtractVecEltPairwiseAdd() argument
125 isSignExtended(Register R,MachineRegisterInfo & MRI) isSignExtended() argument
131 isZeroExtended(Register R,MachineRegisterInfo & MRI) isZeroExtended() argument
137 matchAArch64MulConstCombine(MachineInstr & MI,MachineRegisterInfo & MRI,std::function<void (MachineIRBuilder & B,Register DstReg)> & ApplyFn) matchAArch64MulConstCombine() argument
250 applyAArch64MulConstCombine(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & B,std::function<void (MachineIRBuilder & B,Register DstReg)> & ApplyFn) applyAArch64MulConstCombine() argument
259 matchFoldMergeToZext(MachineInstr & MI,MachineRegisterInfo & MRI) matchFoldMergeToZext() argument
267 applyFoldMergeToZext(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & B,GISelChangeObserver & Observer) applyFoldMergeToZext() argument
280 matchMutateAnyExtToZExt(MachineInstr & MI,MachineRegisterInfo & MRI) matchMutateAnyExtToZExt() argument
297 applyMutateAnyExtToZExt(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & B,GISelChangeObserver & Observer) applyMutateAnyExtToZExt() argument
307 matchSplitStoreZero128(MachineInstr & MI,MachineRegisterInfo & MRI) matchSplitStoreZero128() argument
323 applySplitStoreZero128(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & B,GISelChangeObserver & Observer) applySplitStoreZero128() argument
343 matchOrToBSP(MachineInstr & MI,MachineRegisterInfo & MRI,std::tuple<Register,Register,Register> & MatchInfo) matchOrToBSP() argument
374 applyOrToBSP(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & B,std::tuple<Register,Register,Register> & MatchInfo) applyOrToBSP() argument
539 auto &MRI = MIB.getMF().getRegInfo(); tryOptimizeConsecStores() local
591 auto &MRI = MF.getRegInfo(); optimizeConsecutiveMemOpAddressing() local
[all...] |
| H A D | AArch64InstructionSelector.cpp | 729 auto &MRI = MF.getRegInfo(); getImmedFromMO() local
754 unsupportedBinOp(const MachineInstr & I,const AArch64RegisterBankInfo & RBI,const MachineRegisterInfo & MRI,const AArch64RegisterInfo & TRI) unsupportedBinOp() argument
907 copySubReg(MachineInstr & I,MachineRegisterInfo & MRI,const RegisterBankInfo & RBI,Register SrcReg,const TargetRegisterClass * To,unsigned SubReg) copySubReg() argument
934 getRegClassesForCopy(MachineInstr & I,const TargetInstrInfo & TII,MachineRegisterInfo & MRI,const TargetRegisterInfo & TRI,const RegisterBankInfo & RBI) getRegClassesForCopy() argument
961 selectDebugInstr(MachineInstr & I,MachineRegisterInfo & MRI,const RegisterBankInfo & RBI) selectDebugInstr() argument
991 selectCopy(MachineInstr & I,const TargetInstrInfo & TII,MachineRegisterInfo & MRI,const TargetRegisterInfo & TRI,const RegisterBankInfo & RBI) selectCopy() argument
1161 MachineRegisterInfo &MRI = *MIB.getMRI(); emitSelect() local
1441 getTestBitReg(Register Reg,uint64_t & Bit,bool & Invert,MachineRegisterInfo & MRI) getTestBitReg() argument
1577 MachineRegisterInfo &MRI = *MIB.getMRI(); emitTestBit() local
1650 MachineRegisterInfo &MRI = *MIB.getMRI(); emitCBZ() local
1697 MachineRegisterInfo &MRI = *MIB.getMRI(); tryOptCompareBranchFedByICmp() local
1799 selectCompareBranch(MachineInstr & I,MachineFunction & MF,MachineRegisterInfo & MRI) selectCompareBranch() argument
1834 getVectorShiftImm(Register Reg,MachineRegisterInfo & MRI) getVectorShiftImm() argument
1843 getVectorSHLImm(LLT SrcTy,Register Reg,MachineRegisterInfo & MRI) getVectorSHLImm() argument
1876 selectVectorSHL(MachineInstr & I,MachineRegisterInfo & MRI) selectVectorSHL() argument
1921 selectVectorAshrLshr(MachineInstr & I,MachineRegisterInfo & MRI) selectVectorAshrLshr() argument
2023 MachineRegisterInfo &MRI = MF.getRegInfo(); materializeLargeCMVal() local
2059 MachineRegisterInfo &MRI = MF.getRegInfo(); preISelLower() local
2138 convertPtrAddToAdd(MachineInstr & I,MachineRegisterInfo & MRI) convertPtrAddToAdd() argument
2176 earlySelectSHL(MachineInstr & I,MachineRegisterInfo & MRI) earlySelectSHL() argument
2210 contractCrossBankCopyIntoStore(MachineInstr & I,MachineRegisterInfo & MRI) contractCrossBankCopyIntoStore() argument
2257 MachineRegisterInfo &MRI = MF.getRegInfo(); earlySelect() local
2428 MachineRegisterInfo &MRI = MF.getRegInfo(); select() local
3580 selectMOPS(MachineInstr & GI,MachineRegisterInfo & MRI) selectMOPS() argument
3638 selectBrJT(MachineInstr & I,MachineRegisterInfo & MRI) selectBrJT() argument
3661 selectJumpTable(MachineInstr & I,MachineRegisterInfo & MRI) selectJumpTable() argument
3677 selectTLSGlobalValue(MachineInstr & I,MachineRegisterInfo & MRI) selectTLSGlobalValue() argument
3713 selectVectorICmp(MachineInstr & I,MachineRegisterInfo & MRI) selectVectorICmp() argument
3938 selectMergeValues(MachineInstr & I,MachineRegisterInfo & MRI) selectMergeValues() argument
4038 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); emitExtractVectorElt() local
4096 selectExtractElt(MachineInstr & I,MachineRegisterInfo & MRI) selectExtractElt() argument
4135 selectSplitVectorUnmerge(MachineInstr & I,MachineRegisterInfo & MRI) selectSplitVectorUnmerge() argument
4163 selectUnmergeValues(MachineInstr & I,MachineRegisterInfo & MRI) selectUnmergeValues() argument
4283 selectConcatVectors(MachineInstr & I,MachineRegisterInfo & MRI) selectConcatVectors() argument
4421 MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo(); emitAddSub() local
4496 MachineRegisterInfo *MRI = MIRBuilder.getMRI(); emitADCS() local
4507 MachineRegisterInfo *MRI = MIRBuilder.getMRI(); emitSBCS() local
4516 MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo(); emitCMN() local
4526 MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo(); emitTST() local
4556 MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo(); emitIntegerCompare() local
4571 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); emitCSetForFCmp() local
4598 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); emitFPCompare() local
4644 MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo(); emitVectorConcat() local
4701 auto &MRI = *MIRBuilder.getMRI(); emitCSINC() local
4721 MachineRegisterInfo *MRI = MIB.getMRI(); emitCarryIn() local
4762 selectOverflowOp(MachineInstr & I,MachineRegisterInfo & MRI) selectOverflowOp() argument
4833 canEmitConjunction(Register Val,bool & CanNegate,bool & MustBeFirst,bool WillNegate,MachineRegisterInfo & MRI,unsigned Depth=0) canEmitConjunction() argument
4890 auto &MRI = *MIB.getMRI(); emitConditionalComparison() local
4933 auto &MRI = *MIB.getMRI(); emitConjunctionRec() local
5066 MachineRegisterInfo &MRI = *MIB.getMRI(); tryOptSelect() local
5147 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); tryFoldIntegerCompare() local
5208 selectShuffleVector(MachineInstr & I,MachineRegisterInfo & MRI) selectShuffleVector() argument
5293 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); emitLaneInsert() local
5319 selectUSMovFromExtend(MachineInstr & MI,MachineRegisterInfo & MRI) selectUSMovFromExtend() argument
5384 selectInsertElt(MachineInstr & I,MachineRegisterInfo & MRI) selectInsertElt() argument
5612 selectIndexedExtLoad(MachineInstr & MI,MachineRegisterInfo & MRI) selectIndexedExtLoad() argument
5699 selectIndexedLoad(MachineInstr & MI,MachineRegisterInfo & MRI) selectIndexedLoad() argument
5748 selectIndexedStore(GIndexedStore & I,MachineRegisterInfo & MRI) selectIndexedStore() argument
5797 emitConstantVector(Register Dst,Constant * CV,MachineIRBuilder & MIRBuilder,MachineRegisterInfo & MRI) emitConstantVector() argument
5855 tryOptConstantBuildVec(MachineInstr & I,LLT DstTy,MachineRegisterInfo & MRI) tryOptConstantBuildVec() argument
5886 tryOptBuildVecToSubregToReg(MachineInstr & I,MachineRegisterInfo & MRI) tryOptBuildVecToSubregToReg() argument
5924 selectBuildVector(MachineInstr & I,MachineRegisterInfo & MRI) selectBuildVector() argument
6009 auto &MRI = *MIB.getMRI(); selectVectorLoadIntrinsic() local
6037 auto &MRI = *MIB.getMRI(); selectVectorLoadLaneIntrinsic() local
6088 MachineRegisterInfo &MRI = I.getParent()->getParent()->getRegInfo(); selectVectorStoreIntrinsic() local
6105 MachineRegisterInfo &MRI = I.getParent()->getParent()->getRegInfo(); selectVectorStoreLaneIntrinsic() local
6136 selectIntrinsicWithSideEffects(MachineInstr & I,MachineRegisterInfo & MRI) selectIntrinsicWithSideEffects() argument
6674 selectIntrinsic(MachineInstr & I,MachineRegisterInfo & MRI) selectIntrinsic() argument
6891 MachineRegisterInfo &MRI = Root.getParent()->getMF()->getRegInfo(); selectNegArithImmed() local
6945 MachineRegisterInfo &MRI = Root.getParent()->getMF()->getRegInfo(); selectExtendedSHL() local
7057 MachineRegisterInfo &MRI = Root.getParent()->getMF()->getRegInfo(); selectAddrModeShiftedExtendXReg() local
7096 MachineRegisterInfo &MRI = Root.getParent()->getMF()->getRegInfo(); selectAddrModeRegisterOffset() local
7129 MachineRegisterInfo &MRI = Root.getParent()->getMF()->getRegInfo(); selectAddrModeXRO() local
7203 MachineRegisterInfo &MRI = Root.getParent()->getMF()->getRegInfo(); selectAddrModeWRO() local
7270 MachineRegisterInfo &MRI = selectAddrModeUnscaled() local
7344 MachineRegisterInfo &MRI = MF.getRegInfo(); selectAddrModeIndexed() local
7422 MachineRegisterInfo &MRI = selectShiftedRegister() local
7456 getExtendTypeForInst(MachineInstr & MI,MachineRegisterInfo & MRI,bool IsLoadStore) const getExtendTypeForInst() argument
7517 MachineRegisterInfo &MRI = *MIB.getMRI(); moveScalarRegClass() local
7537 MachineRegisterInfo &MRI = selectArithExtendedRegister() local
7602 MachineRegisterInfo &MRI = selectExtractHigh() local
7636 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); renderTruncImm() local
7711 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); isDef32() local
7733 fixupPHIOpBanks(MachineInstr & MI,MachineRegisterInfo & MRI,const AArch64RegisterBankInfo & RBI) fixupPHIOpBanks() argument
7768 MachineRegisterInfo &MRI = MF.getRegInfo(); processPHIs() local
[all...] |
| H A D | AArch64PreLegalizerCombiner.cpp | 50 bool matchFConstantToConstant(MachineInstr &MI, MachineRegisterInfo &MRI) { in matchFConstantToConstant() argument
76 bool matchICmpRedundantTrunc(MachineInstr &MI, MachineRegisterInfo &MRI, in matchICmpRedundantTrunc() argument
105 void applyICmpRedundantTrunc(MachineInstr &MI, MachineRegisterInfo &MRI, in applyICmpRedundantTrunc() argument
126 matchFoldGlobalOffset(MachineInstr & MI,MachineRegisterInfo & MRI,std::pair<uint64_t,uint64_t> & MatchInfo) matchFoldGlobalOffset() argument
193 applyFoldGlobalOffset(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & B,GISelChangeObserver & Observer,std::pair<uint64_t,uint64_t> & MatchInfo) applyFoldGlobalOffset() argument
235 matchExtAddvToUdotAddv(MachineInstr & MI,MachineRegisterInfo & MRI,const AArch64Subtarget & STI,std::tuple<Register,Register,bool> & MatchInfo) matchExtAddvToUdotAddv() argument
290 applyExtAddvToUdotAddv(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & Builder,GISelChangeObserver & Observer,const AArch64Subtarget & STI,std::tuple<Register,Register,bool> & MatchInfo) applyExtAddvToUdotAddv() argument
415 matchExtUaddvToUaddlv(MachineInstr & MI,MachineRegisterInfo & MRI,std::pair<Register,bool> & MatchInfo) matchExtUaddvToUaddlv() argument
447 applyExtUaddvToUaddlv(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & B,GISelChangeObserver & Observer,std::pair<Register,bool> & MatchInfo) applyExtUaddvToUaddlv() argument
587 auto &MRI = *B.getMRI(); tryToSimplifyUADDO() local
[all...] |
| H A D | AArch64LegalizerInfo.cpp | 1311 return legalizeLoadStore(MI, MRI, MIRBuilder, Observer); in legalizeSmallCMGlobalValue() argument
1191 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); legalizeCustom() local
1241 legalizeFunnelShift(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & MIRBuilder,GISelChangeObserver & Observer,LegalizerHelper & Helper) const legalizeFunnelShift() argument
1294 legalizeRotate(MachineInstr & MI,MachineRegisterInfo & MRI,LegalizerHelper & Helper) const legalizeRotate() argument
1433 MachineRegisterInfo &MRI = *MIB.getMRI(); legalizeIntrinsic() local
1471 MachineRegisterInfo &MRI = *MIB.getMRI(); legalizeIntrinsic() local
1547 legalizeShlAshrLshr(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & MIRBuilder,GISelChangeObserver & Observer) const legalizeShlAshrLshr() argument
1570 matchLDPSTPAddrMode(Register Root,Register & Base,int & Offset,MachineRegisterInfo & MRI) matchLDPSTPAddrMode() argument
1586 legalizeLoadStore(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & MIRBuilder,GISelChangeObserver & Observer) const legalizeLoadStore() argument
1678 legalizeVaArg(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & MIRBuilder) const legalizeVaArg() argument
1726 legalizeBitfieldExtract(MachineInstr & MI,MachineRegisterInfo & MRI,LegalizerHelper & Helper) const legalizeBitfieldExtract() argument
1734 legalizeCTPOP(MachineInstr & MI,MachineRegisterInfo & MRI,LegalizerHelper & Helper) const legalizeCTPOP() argument
1845 legalizeAtomicCmpxchg128(MachineInstr & MI,MachineRegisterInfo & MRI,LegalizerHelper & Helper) const legalizeAtomicCmpxchg128() argument
1944 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); legalizeCTTZ() local
1973 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); legalizeFCopySign() local
2031 legalizeExtractVectorElt(MachineInstr & MI,MachineRegisterInfo & MRI,LegalizerHelper & Helper) const legalizeExtractVectorElt() argument
2045 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); legalizeDynStackAlloc() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86InstructionSelector.cpp | 353 MachineRegisterInfo &MRI = MF.getRegInfo(); select() local
524 X86SelectAddress(const MachineInstr & I,const MachineRegisterInfo & MRI,X86AddressMode & AM) X86SelectAddress() argument
550 selectLoadStoreOp(MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) const selectLoadStoreOp() argument
610 selectFrameIndexOrGep(MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) const selectFrameIndexOrGep() argument
638 selectGlobalValue(MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) const selectGlobalValue() argument
684 selectConstant(MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) const selectConstant() argument
741 selectTurnIntoCOPY(MachineInstr & I,MachineRegisterInfo & MRI,const unsigned DstReg,const TargetRegisterClass * DstRC,const unsigned SrcReg,const TargetRegisterClass * SrcRC) const selectTurnIntoCOPY() argument
756 selectTruncOrPtrToInt(MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) const selectTruncOrPtrToInt() argument
822 selectZext(MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) const selectZext() argument
887 selectAnyext(MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) const selectAnyext() argument
942 selectCmp(MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) const selectCmp() argument
993 selectFCmp(MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) const selectFCmp() argument
1084 selectUAddSub(MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) const selectUAddSub() argument
1190 selectExtract(MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) const selectExtract() argument
1248 emitExtractSubreg(unsigned DstReg,unsigned SrcReg,MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) const emitExtractSubreg() argument
1286 emitInsertSubreg(unsigned DstReg,unsigned SrcReg,MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) const emitInsertSubreg() argument
1323 selectInsert(MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) const selectInsert() argument
1381 selectUnmergeValues(MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) selectUnmergeValues() argument
1406 selectMergeValues(MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) selectMergeValues() argument
1455 selectCondBranch(MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) const selectCondBranch() argument
1476 materializeFP(MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) const materializeFP() argument
1570 selectMulDivRem(MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) const selectMulDivRem() argument
1798 selectSelect(MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) const selectSelect() argument
1841 selectIntrinsicWSideEffects(MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) const selectIntrinsicWSideEffects() argument
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMAsmBackendDarwin.h | 19 const MCRegisterInfo &MRI; variable
24 const MCRegisterInfo &MRI) in ARMAsmBackendDarwin() argument
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVOptWInstrs.cpp | 110 hasAllNBitUsers(const MachineInstr & OrigMI,const RISCVSubtarget & ST,const MachineRegisterInfo & MRI,unsigned OrigBits) hasAllNBitUsers() argument
334 hasAllWUsers(const MachineInstr & OrigMI,const RISCVSubtarget & ST,const MachineRegisterInfo & MRI) hasAllWUsers() argument
341 isSignExtendingOpW(const MachineInstr & MI,const MachineRegisterInfo & MRI) isSignExtendingOpW() argument
385 isSignExtendedW(Register SrcReg,const RISCVSubtarget & ST,const MachineRegisterInfo & MRI,SmallPtrSetImpl<MachineInstr * > & FixableDef) isSignExtendedW() argument
624 removeSExtWInstrs(MachineFunction & MF,const RISCVInstrInfo & TII,const RISCVSubtarget & ST,MachineRegisterInfo & MRI) removeSExtWInstrs() argument
676 stripWSuffixes(MachineFunction & MF,const RISCVInstrInfo & TII,const RISCVSubtarget & ST,MachineRegisterInfo & MRI) stripWSuffixes() argument
707 MachineRegisterInfo &MRI = MF.getRegInfo(); runOnMachineFunction() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | CodeGenCommonISel.cpp | 210 static MachineOperand *getSalvageOpsForCopy(const MachineRegisterInfo &MRI, in getSalvageOpsForCopy() argument
217 static MachineOperand *getSalvageOpsForTrunc(const MachineRegisterInfo &MRI, in getSalvageOpsForTrunc() argument
236 static MachineOperand *salvageDebugInfoImpl(const MachineRegisterInfo &MRI, in salvageDebugInfoImpl() argument
249 void llvm::salvageDebugInfoForDbgValue(const MachineRegisterInfo &MRI, in salvageDebugInfoForDbgValue() argument
|
| H A D | LivePhysRegs.cpp | 141 bool LivePhysRegs::available(const MachineRegisterInfo &MRI, in available()
176 const MachineRegisterInfo &MRI = MF.getRegInfo(); in addCalleeSavedRegs() local
251 const MachineRegisterInfo &MRI = MF.getRegInfo(); in computeLiveIns() local
262 const MachineRegisterInfo &MRI = MF.getRegInfo(); in addLiveIns() local
278 const MachineRegisterInfo &MRI = MF.getRegInfo(); in recomputeLivenessFlags() local
|
| H A D | MIRVRegNamerUtils.h | 48 MachineRegisterInfo &MRI; variable
85 VRegRenamer(MachineRegisterInfo &MRI) : MRI(MRI) {} in VRegRenamer()
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCCallLowering.h | 42 MachineRegisterInfo &MRI) in PPCIncomingValueHandler()
67 FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI) in FormalArgHandler()
|
| H A D | PPCRegisterBankInfo.cpp | 82 const MachineRegisterInfo &MRI = MF.getRegInfo(); getInstrMapping() local
289 hasFPConstraints(const MachineInstr & MI,const MachineRegisterInfo & MRI,const TargetRegisterInfo & TRI,unsigned Depth) const hasFPConstraints() argument
332 onlyUsesFP(const MachineInstr & MI,const MachineRegisterInfo & MRI,const TargetRegisterInfo & TRI,unsigned Depth) const onlyUsesFP() argument
351 onlyDefinesFP(const MachineInstr & MI,const MachineRegisterInfo & MRI,const TargetRegisterInfo & TRI,unsigned Depth) const onlyDefinesFP() argument
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/include/llvm/Support/ |
| H A D | ModRef.h | 39 [[nodiscard]] inline bool isNoModRef(const ModRefInfo MRI) { in isNoModRef()
42 [[nodiscard]] inline bool isModOrRefSet(const ModRefInfo MRI) { in isModOrRefSet()
45 [[nodiscard]] inline bool isModAndRefSet(const ModRefInfo MRI) { in isModAndRefSet()
48 [[nodiscard]] inline bool isModSet(const ModRefInfo MRI) { in isModSet()
51 [[nodiscard]] inline bool isRefSet(const ModRefInfo MRI) { in isRefSet()
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFMISimplifyPatchable.cpp | 127 checkADDrr(MachineRegisterInfo * MRI,MachineOperand * RelocOp,const GlobalValue * GVal) checkADDrr() argument
175 checkShift(MachineRegisterInfo * MRI,MachineBasicBlock & MBB,MachineOperand * RelocOp,const GlobalValue * GVal,unsigned Opcode) checkShift() argument
189 processCandidate(MachineRegisterInfo * MRI,MachineBasicBlock & MBB,MachineInstr & MI,Register & SrcReg,Register & DstReg,const GlobalValue * GVal,bool IsAma) processCandidate() argument
224 processDstReg(MachineRegisterInfo * MRI,Register & DstReg,Register & SrcReg,const GlobalValue * GVal,bool doSrcRegProp,bool IsAma) processDstReg() argument
285 processInst(MachineRegisterInfo * MRI,MachineInstr * Inst,MachineOperand * RelocOp,const GlobalValue * GVal) processInst() argument
305 MachineRegisterInfo *MRI = &MF->getRegInfo(); removeLD() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVPreLegalizer.cpp | 42 MachineRegisterInfo &MRI = MF.getRegInfo(); addConstantsToTrack() local
100 MachineRegisterInfo &MRI = MF.getRegInfo(); foldConstantsIntoIntrinsics() local
169 propagateSPIRVType(MachineInstr * MI,SPIRVGlobalRegistry * GR,MachineRegisterInfo & MRI,MachineIRBuilder & MIB) propagateSPIRVType() argument
220 insertAssignInstr(Register Reg,Type * Ty,SPIRVType * SpirvTy,SPIRVGlobalRegistry * GR,MachineIRBuilder & MIB,MachineRegisterInfo & MRI) insertAssignInstr() argument
253 MachineRegisterInfo &MRI = MF.getRegInfo(); generateAssignInstrs() local
342 createNewIdReg(Register ValReg,unsigned Opcode,MachineRegisterInfo & MRI,const SPIRVGlobalRegistry & GR) createNewIdReg() argument
370 processInstr(MachineInstr & MI,MachineIRBuilder & MIB,MachineRegisterInfo & MRI,SPIRVGlobalRegistry * GR) processInstr() argument
396 MachineRegisterInfo &MRI = MF.getRegInfo(); processInstrsWithTypeFolding() local
461 MachineRegisterInfo &MRI = MF.getRegInfo(); processSwitches() local
[all...] |
| H A D | SPIRVInstrInfo.cpp | 50 auto &MRI = MI.getMF()->getRegInfo(); isTypeDeclInstr() local
243 auto &MRI = I->getMF()->getRegInfo(); copyPhysReg() local
251 auto &MRI = MI.getMF()->getRegInfo(); expandPostRAPseudo() local
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVRegisterBankInfo.cpp | 168 hasFPConstraints(const MachineInstr & MI,const MachineRegisterInfo & MRI,const TargetRegisterInfo & TRI) const hasFPConstraints() argument
182 onlyUsesFP(const MachineInstr & MI,const MachineRegisterInfo & MRI,const TargetRegisterInfo & TRI) const onlyUsesFP() argument
197 onlyDefinesFP(const MachineInstr & MI,const MachineRegisterInfo & MRI,const TargetRegisterInfo & TRI) const onlyDefinesFP() argument
211 anyUseOnlyUseFP(Register Def,const MachineRegisterInfo & MRI,const TargetRegisterInfo & TRI) const anyUseOnlyUseFP() argument
231 const MachineRegisterInfo &MRI = MF.getRegInfo(); getInstrMapping() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | CSEInfo.h | 75 MachineRegisterInfo *MRI = nullptr; variable
171 const MachineRegisterInfo &MRI; variable
174 GISelInstProfileBuilder(FoldingSetNodeID &ID, const MachineRegisterInfo &MRI) in GISelInstProfileBuilder()
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsRegisterBankInfo.cpp | 180 addDefUses(Register Reg,const MachineRegisterInfo & MRI) addDefUses() argument
195 addUseDef(Register Reg,const MachineRegisterInfo & MRI) addUseDef() argument
206 const MachineRegisterInfo &MRI = MF.getRegInfo(); skipCopiesOutgoing() local
220 const MachineRegisterInfo &MRI = MF.getRegInfo(); skipCopiesIncoming() local
233 const MachineRegisterInfo &MRI = MI->getMF()->getRegInfo(); AmbiguousRegDefUseContainer() local
367 const MachineRegisterInfo &MRI = MF.getRegInfo(); setTypesAccordingToPhysicalRegister() local
433 const MachineRegisterInfo &MRI = MF.getRegInfo(); getInstrMapping() local
739 MachineRegisterInfo &MRI = OpdMapper.getMRI(); applyMappingImpl() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNRegPressure.cpp | 39 const MachineRegisterInfo &MRI) { in getRegKind() argument
53 const MachineRegisterInfo &MRI) { in inc() argument
158 getDefRegMask(const MachineOperand & MO,const MachineRegisterInfo & MRI) getDefRegMask() argument
172 collectVirtualRegUses(SmallVectorImpl<RegisterMaskPair> & RegMaskPairs,const MachineInstr & MI,const LiveIntervals & LIS,const MachineRegisterInfo & MRI) collectVirtualRegUses() argument
208 getLiveLaneMask(unsigned Reg,SlotIndex SI,const LiveIntervals & LIS,const MachineRegisterInfo & MRI) getLiveLaneMask() argument
213 getLiveLaneMask(const LiveInterval & LI,SlotIndex SI,const MachineRegisterInfo & MRI) getLiveLaneMask() argument
229 getLiveRegs(SlotIndex SI,const LiveIntervals & LIS,const MachineRegisterInfo & MRI) getLiveRegs() argument
486 print(const GCNRPTracker::LiveRegSet & LiveRegs,const MachineRegisterInfo & MRI) print() argument
515 getRegLiveThroughMask(const MachineRegisterInfo & MRI,const LiveIntervals & LIS,Register Reg,SlotIndex Begin,SlotIndex End,LaneBitmask Mask=LaneBitmask::getAll ()) getRegLiveThroughMask() argument
541 const MachineRegisterInfo &MRI = MF.getRegInfo(); runOnMachineFunction() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXPeephole.cpp | 84 const auto &MRI = MF.getRegInfo(); in isCVTAToLocalCombinationCandidate() local
112 const auto &MRI = MF.getRegInfo(); in CombineCVTAToLocal() local
157 const auto &MRI = MF.getRegInfo(); in runOnMachineFunction() local
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyPeephole.cpp | 63 MachineRegisterInfo &MRI) { in maybeRewriteToDrop()
78 MachineRegisterInfo &MRI, in maybeRewriteToFallthrough()
118 MachineRegisterInfo &MRI = MF.getRegInfo(); in runOnMachineFunction() local
|