Lines Matching defs:MRI
78 bool selectLoadStoreOp(MachineInstr &I, MachineRegisterInfo &MRI,
80 bool selectFrameIndexOrGep(MachineInstr &I, MachineRegisterInfo &MRI,
82 bool selectGlobalValue(MachineInstr &I, MachineRegisterInfo &MRI,
84 bool selectConstant(MachineInstr &I, MachineRegisterInfo &MRI,
86 bool selectTruncOrPtrToInt(MachineInstr &I, MachineRegisterInfo &MRI,
88 bool selectZext(MachineInstr &I, MachineRegisterInfo &MRI,
90 bool selectAnyext(MachineInstr &I, MachineRegisterInfo &MRI,
92 bool selectCmp(MachineInstr &I, MachineRegisterInfo &MRI,
94 bool selectFCmp(MachineInstr &I, MachineRegisterInfo &MRI,
96 bool selectUAddSub(MachineInstr &I, MachineRegisterInfo &MRI,
98 bool selectDebugInstr(MachineInstr &I, MachineRegisterInfo &MRI) const;
99 bool selectCopy(MachineInstr &I, MachineRegisterInfo &MRI) const;
100 bool selectUnmergeValues(MachineInstr &I, MachineRegisterInfo &MRI,
102 bool selectMergeValues(MachineInstr &I, MachineRegisterInfo &MRI,
104 bool selectInsert(MachineInstr &I, MachineRegisterInfo &MRI,
106 bool selectExtract(MachineInstr &I, MachineRegisterInfo &MRI,
108 bool selectCondBranch(MachineInstr &I, MachineRegisterInfo &MRI,
110 bool selectTurnIntoCOPY(MachineInstr &I, MachineRegisterInfo &MRI,
115 bool materializeFP(MachineInstr &I, MachineRegisterInfo &MRI,
117 bool selectImplicitDefOrPHI(MachineInstr &I, MachineRegisterInfo &MRI) const;
118 bool selectMulDivRem(MachineInstr &I, MachineRegisterInfo &MRI,
120 bool selectSelect(MachineInstr &I, MachineRegisterInfo &MRI,
125 MachineRegisterInfo &MRI, MachineFunction &MF) const;
128 MachineRegisterInfo &MRI, MachineFunction &MF) const;
132 MachineRegisterInfo &MRI) const;
212 MachineRegisterInfo &MRI) const {
213 const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI);
248 MachineRegisterInfo &MRI) const {
257 LLT Ty = MRI.getType(Reg);
258 const RegClassOrRegBank &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
270 RBI.constrainGenericRegister(Reg, *RC, MRI);
278 MachineRegisterInfo &MRI) const {
280 const unsigned DstSize = RBI.getSizeInBits(DstReg, MRI, TRI);
281 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI);
284 const unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI);
285 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI);
294 getRegClass(MRI.getType(SrcReg), SrcRegBank);
299 Register ExtSrc = MRI.createVirtualRegister(DstRC);
320 DstSize <= RBI.getSizeInBits(SrcReg, MRI, TRI))) &&
324 getRegClass(MRI.getType(DstReg), DstRegBank);
342 const TargetRegisterClass *OldRC = MRI.getRegClassOrNull(DstReg);
344 if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
360 MachineRegisterInfo &MRI = MF.getRegInfo();
370 return selectCopy(I, MRI);
373 return selectDebugInstr(I, MRI);
392 return selectLoadStoreOp(I, MRI, MF);
395 return selectFrameIndexOrGep(I, MRI, MF);
397 return selectGlobalValue(I, MRI, MF);
399 return selectConstant(I, MRI, MF);
401 return materializeFP(I, MRI, MF);
404 return selectTruncOrPtrToInt(I, MRI, MF);
406 return selectCopy(I, MRI);
408 return selectZext(I, MRI, MF);
410 return selectAnyext(I, MRI, MF);
412 return selectCmp(I, MRI, MF);
414 return selectFCmp(I, MRI, MF);
419 return selectUAddSub(I, MRI, MF);
421 return selectUnmergeValues(I, MRI, MF);
424 return selectMergeValues(I, MRI, MF);
426 return selectExtract(I, MRI, MF);
428 return selectInsert(I, MRI, MF);
430 return selectCondBranch(I, MRI, MF);
433 return selectImplicitDefOrPHI(I, MRI);
441 return selectMulDivRem(I, MRI, MF);
443 return selectSelect(I, MRI, MF);
535 const MachineRegisterInfo &MRI,
538 assert(MRI.getType(I.getOperand(0).getReg()).isPointer() &&
542 if (auto COff = getIConstantVRegSExtVal(I.getOperand(2).getReg(), MRI)) {
561 MachineRegisterInfo &MRI,
569 LLT Ty = MRI.getType(DefReg);
570 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
596 const MachineInstr *Ptr = MRI.getVRegDef(I.getOperand(1).getReg());
619 X86SelectAddress(*Ptr, MRI, AM);
644 MachineRegisterInfo &MRI,
652 LLT Ty = MRI.getType(DefReg);
672 MachineRegisterInfo &MRI,
705 LLT Ty = MRI.getType(DefReg);
718 MachineRegisterInfo &MRI,
724 LLT Ty = MRI.getType(DefReg);
726 if (RBI.getRegBank(DefReg, MRI, TRI)->getID() != X86::GPRRegBankID)
775 MachineInstr &I, MachineRegisterInfo &MRI, const unsigned DstReg,
779 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
780 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
790 MachineRegisterInfo &MRI,
799 const LLT DstTy = MRI.getType(DstReg);
800 const LLT SrcTy = MRI.getType(SrcReg);
802 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
803 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI);
821 return selectTurnIntoCOPY(I, MRI, DstReg, DstRC, SrcReg, SrcRC);
842 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
843 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
856 MachineRegisterInfo &MRI,
863 const LLT DstTy = MRI.getType(DstReg);
864 const LLT SrcTy = MRI.getType(SrcReg);
897 MRI.createVirtualRegister(getRegClass(DstTy, DstReg, MRI));
901 DefReg = MRI.createVirtualRegister(getRegClass(DstTy, DstReg, MRI));
921 MachineRegisterInfo &MRI,
928 const LLT DstTy = MRI.getType(DstReg);
929 const LLT SrcTy = MRI.getType(SrcReg);
931 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
932 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI);
947 return selectTurnIntoCOPY(I, MRI, SrcReg, SrcRC, DstReg, DstRC);
952 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
953 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
976 MachineRegisterInfo &MRI,
992 LLT Ty = MRI.getType(LHS);
1027 MachineRegisterInfo &MRI,
1054 LLT Ty = MRI.getType(LhsReg);
1069 *getRegClass(LLT::scalar(8), *RBI.getRegBank(ResultReg, MRI, TRI)), MRI);
1076 Register FlagReg1 = MRI.createVirtualRegister(&X86::GR8RegClass);
1077 Register FlagReg2 = MRI.createVirtualRegister(&X86::GR8RegClass);
1118 MachineRegisterInfo &MRI,
1135 const LLT DstTy = MRI.getType(DstReg);
1169 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
1177 MachineInstr *Def = MRI.getVRegDef(CarryInReg);
1180 Def = MRI.getVRegDef(CarryInReg);
1193 if (!RBI.constrainGenericRegister(CarryInReg, *DstRC, MRI))
1197 } else if (auto val = getIConstantVRegVal(CarryInReg, MRI)) {
1216 !RBI.constrainGenericRegister(CarryOutReg, *DstRC, MRI))
1224 MachineRegisterInfo &MRI,
1233 const LLT DstTy = MRI.getType(DstReg);
1234 const LLT SrcTy = MRI.getType(SrcReg);
1245 if (!emitExtractSubreg(DstReg, SrcReg, I, MRI, MF))
1282 MachineRegisterInfo &MRI,
1284 const LLT DstTy = MRI.getType(DstReg);
1285 const LLT SrcTy = MRI.getType(SrcReg);
1301 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstReg, MRI);
1302 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcReg, MRI);
1306 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
1307 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
1320 MachineRegisterInfo &MRI,
1322 const LLT DstTy = MRI.getType(DstReg);
1323 const LLT SrcTy = MRI.getType(SrcReg);
1340 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcReg, MRI);
1341 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstReg, MRI);
1343 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
1344 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
1357 MachineRegisterInfo &MRI,
1366 const LLT DstTy = MRI.getType(DstReg);
1367 const LLT InsertRegTy = MRI.getType(InsertReg);
1376 if (Index == 0 && MRI.getVRegDef(SrcReg)->isImplicitDef()) {
1378 if (!emitInsertSubreg(DstReg, InsertReg, I, MRI, MF))
1415 MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) {
1422 unsigned DefSize = MRI.getType(I.getOperand(0).getReg()).getSizeInBits();
1440 MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) {
1449 const LLT DstTy = MRI.getType(DstReg);
1450 const LLT SrcTy = MRI.getType(SrcReg0);
1453 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI);
1456 Register DefReg = MRI.createGenericVirtualRegister(DstTy);
1457 MRI.setRegBank(DefReg, RegBank);
1458 if (!emitInsertSubreg(DefReg, I.getOperand(1).getReg(), I, MRI, MF))
1462 Register Tmp = MRI.createGenericVirtualRegister(DstTy);
1463 MRI.setRegBank(Tmp, RegBank);
1489 MachineRegisterInfo &MRI,
1510 MachineRegisterInfo &MRI,
1521 const LLT DstTy = MRI.getType(DstReg);
1522 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI);
1540 Register AddrReg = MRI.createVirtualRegister(&X86::GR64RegClass);
1578 MachineInstr &I, MachineRegisterInfo &MRI) const {
1585 if (!MRI.getRegClassOrNull(DstReg)) {
1586 const LLT DstTy = MRI.getType(DstReg);
1587 const TargetRegisterClass *RC = getRegClass(DstTy, DstReg, MRI);
1589 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
1605 MachineRegisterInfo &MRI,
1621 const LLT RegTy = MRI.getType(DstReg);
1622 assert(RegTy == MRI.getType(Op1Reg) && RegTy == MRI.getType(Op2Reg) &&
1625 const RegisterBank *RegRB = RBI.getRegBank(DstReg, MRI, TRI);
1747 if (!RBI.constrainGenericRegister(Op1Reg, *RegRC, MRI) ||
1748 !RBI.constrainGenericRegister(Op2Reg, *RegRC, MRI) ||
1749 !RBI.constrainGenericRegister(DstReg, *RegRC, MRI)) {
1766 Register Zero32 = MRI.createVirtualRegister(&X86::GR32RegClass);
1804 Register SourceSuperReg = MRI.createVirtualRegister(&X86::GR16RegClass);
1805 Register ResultSuperReg = MRI.createVirtualRegister(&X86::GR16RegClass);
1830 MachineRegisterInfo &MRI,
1839 LLT Ty = MRI.getType(DstReg);
1862 const TargetRegisterClass *DstRC = getRegClass(Ty, DstReg, MRI);
1863 if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {