| /llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 755 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth() argument
796 const MachineInstr &LdSt, SmallVectorImp in getMemOperandsWithOffsetWidth() argument
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| /llvm-project/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCInstructionSelector.cpp | 730 GLoadStore &LdSt = cast<GLoadStore>(I); in select() local
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| /llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerCombiner.cpp | 715 if (auto *LdSt = dyn_cast<GLoadStore>(&MI); optimizeConsecutiveMemOpAddressing() local
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| H A D | AArch64InstructionSelector.cpp | 2859 GLoadStore &LdSt = cast<GLoadStore>(I); select() local
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| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 2838 getMemOperandsWithOffsetWidth(const MachineInstr & LdSt,SmallVectorImpl<const MachineOperand * > & BaseOps,int64_t & Offset,bool & OffsetIsScalable,LocationSize & Width,const TargetRegisterInfo * TRI) const getMemOperandsWithOffsetWidth() argument
2849 isLdStSafeToCluster(const MachineInstr & LdSt,const TargetRegisterInfo * TRI) isLdStSafeToCluster() argument
5527 getMemOperandWithOffsetWidth(const MachineInstr & LdSt,const MachineOperand * & BaseReg,int64_t & Offset,LocationSize & Width,const TargetRegisterInfo * TRI) const getMemOperandWithOffsetWidth() argument
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| /llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.cpp | 2608 getMemOperandsWithOffsetWidth(const MachineInstr & LdSt,SmallVectorImpl<const MachineOperand * > & BaseOps,int64_t & Offset,bool & OffsetIsScalable,LocationSize & Width,const TargetRegisterInfo * TRI) const getMemOperandsWithOffsetWidth() argument
2713 getMemOperandWithOffsetWidth(const MachineInstr & LdSt,const MachineOperand * & BaseReg,int64_t & Offset,LocationSize & Width,const TargetRegisterInfo * TRI) const getMemOperandWithOffsetWidth() argument
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| /llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelDAGToDAG.cpp | 1526 auto *LdSt = dyn_cast<LSBaseSDNode>(MemAccess); storeLoadIsAligned() local
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| /llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 1167 LLT MemTy = LdSt.getMMO().getMemoryType(); in findPostIndexCandidate() argument
1263 findPreIndexCandidate(GLoadStore & LdSt,Register & Addr,Register & Base,Register & Offset) findPreIndexCandidate() argument
1427 auto &LdSt = cast<GLoadStore>(MI); matchCombineIndexedLoadStore() local
1735 if (auto *LdSt = dyn_cast<GLoadStore>(&UseMI)) { matchPtrAddImmedChain() local
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| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 2700 getMemOperandsWithOffsetWidth(const MachineInstr & LdSt,SmallVectorImpl<const MachineOperand * > & BaseOps,int64_t & Offset,bool & OffsetIsScalable,LocationSize & Width,const TargetRegisterInfo * TRI) const getMemOperandsWithOffsetWidth() argument
3491 getMemOperandWithOffsetWidth(const MachineInstr & LdSt,const MachineOperand * & BaseOp,int64_t & Offset,bool & OffsetIsScalable,TypeSize & Width,const TargetRegisterInfo * TRI) const getMemOperandWithOffsetWidth() argument
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| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 3073 getMemOperandsWithOffsetWidth(const MachineInstr & LdSt,SmallVectorImpl<const MachineOperand * > & BaseOps,int64_t & Offset,bool & OffsetIsScalable,LocationSize & Width,const TargetRegisterInfo * TRI) const getMemOperandsWithOffsetWidth() argument
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| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1093 LSBaseSDNode *LdSt = cast<LSBaseSDNode>(Op); SelectAddrMode6Offset() local
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| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 360 if (!LdSt.mayLoadOrStore()) in getMemOperandsWithOffsetWidth() argument
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